50.3.4 I/O Ports

Table 50-4.
Standard Operating Conditions (unless otherwise stated)
Param. No.	Sym.	Device Characteristics	Min.	Typ.†	Max.	Units	Conditions
Input Low-Voltage
		I/O PORT:
D300	V_IL	with LVBUF (TTL compatible)	—	—	0.75	V
D302	V_IL	with Schmitt Trigger buffer	—	—	0.2 V_DD	V	2.0V ≤ V_DD ≤ 5.5V
D302A	V_IL	with Schmitt Trigger buffer	—	—	0.3 V_DDIOx	V	2.0V ≤ V_DDIOx ≤ 5.5V
D303	V_IL	with I²C levels	—	—	0.3 V_DD	V	2.0V ≤ V_DD ≤ 5.5V
D304	V_IL	with SMBus 2.0	—	—	0.8	V	2.7V ≤ V_DD ≤ 5.5V
D305	V_IL	with SMBus 3.0	—	—	0.8	V
D306	V_IL	MCLR	—	—	0.2 V_DD	V
High/Low-Voltage
		I/O PORT:
D320	V_IH	with LVBUF (TTL compatible)	1.5	—	—	V
D322	V_IH	with Schmitt Trigger buffer	0.8 V_DD	—	—	V	2.0V ≤ V_DD ≤ 5.5V
D322A	V_IH	with Schmitt Trigger buffer	0.8 V_DDIOx	—	—	V	2.0V ≤ V_DDIOx ≤ 5.5V
D323	V_IH	with I²C levels	0.7 V_DD	—	—	V	2.0V ≤ V_DDIOx ≤ 5.5V
D324	V_IH	with SMBus 2.0	2.1	—	—	V	2.7V ≤ V_DD ≤ 5.5V; 2.7V ≤ V_DDIOx ≤ 5.5V
D325	V_IH	with SMBus 3.0	1.35	—	—	V	0°C ≤ TA ≤ 125°C; 2.5V ≤ V_DD ≤ 5.5V
D325A	V_IH	with SMBus 3.0	1.45	—	—	V	-40°C ≤ TA ≤ 125°C; 1.8V ≤ V_DD ≤ 5.5V
D326	V_IH	MCLR	0.7 V_DD	—	—	V
Input Leakage Current⁽¹⁾
D340	I_IL	All I/O Pins (V_DD domain)	—	±5	±125	nA	V_SS ≤ V_PIN ≤ V_DD; Pin at high-impedance, 85°C
D340A*	I_IL	All I/O Pins (MVIO domain without I²C/SMBus Functionality)	—	±5	±125	nA	V_SS ≤ V_PIN ≤ V_DDIOx (MVIO domain); Pin at high-impedance, 85°C
D341	I_IL	All I/O Pins (V_DD domain)	—	±5	±1000	nA	V_SS ≤ V_PIN ≤ V_DD; Pin at high-impedance, 125°C
D341A*	I_IL	All I/O Pins (MVIO domain without I²C/SMBus Functionality)	—	±5	±1000	nA	V_SS ≤ V_PIN ≤ V_DDIOx (MVIO domain); Pin at high-impedance, 125°C
D342	I_IL	MCLR⁽²⁾	—	±50	±200	nA	V_SS ≤ V_PIN ≤ V_DD, Pin at high-impedance, 85°C
Weak Pull-up Current
D350	I_PUR		80	140	200	μA	V_DD = 3.0V, V_PIN = V_SS
Output Low-Voltage
D360	V_OL	with GPIO driver (all pins on V_DD and MVIO domains)	—	—	0.6	V	I_OL = 10.0 mA, V_DD and MVIO domains = 3.0V
Output High-Voltage
D370	V_OH	with GPIO driver (all pins on V_DD and MVIO domains)	V_DD - 0.7	—	—	V	I_OH = 6 mA V_DD and MVIO domains = 3.0V;
Load Capacitance
D380*	C_IO	All I/O Pins (V_DD and MVIO domains)	—	5	50	pF
Input Capacitance
D390*	C_I	All I/O Pins (V_DD and MVIO domains)	—	—	5	pF
* These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.