5 Behavior

This UDC stack implementation is based on an interrupt driven scheme. This solution ensures low latency, does not require any wait loop, and ensures OS compatibility.

Depending on the USB interrupt routine priority, the USB interrupt can be blocked by other interrupt routines with higher priority, or a critical code section. The USB hardware and software does not have any timing requirements except for the USB “Set Address” request (performed during USB enumeration phase to assign the USB address). The user must take care that the USB interrupt is not blocked during the "Set Address" request for longer than the maximum delay given in the table below.

Table 5-1. Set Address Timing
USB Host		Maximum Delay⁽¹⁾
Specification		2ms
USB org certification tools		12ms
Windows® XP		48ms
Windows 7, Vista		32ms
Mac Mini OSX 10.5.8		77ms
Ubuntu 8.04, Ubuntu 9, Open Suse 11.1		29ms
Fedora 9, Fedora 10		24ms

Note: ⁽¹⁾ These numbers will depend on USB host hardware, and is only a ballpark number for reference. These numbers include the time for setup retry.

USB hosts uses a timeout to reset a non-answering USB device (this time is not specified by the USB specification). The table below lists examples of operating system's timeout:

Table 5-2. OS Timeout
USB host	Timeout
	Control Endpoint		Mass Storage
	Data Phase	ZLP Phase	CBW	Data Read	CSW
Specification	No timeout
Windows XP	5.3s	5.3s	19s	9.3s	9.3s
Windows 7, Vista	5.3s	5.3s	19s	160s/60s	160s/60s
Mac Mini OSX 10.5.8	5.9s	5.6s	11s	31s	22s
Ubuntu 8.04, Ubuntu 9, Open Suse 11.1	5s	5s	30s	30s	30s
Fedora 9, Fedora 10	5s	5s	30s	60s	30s

The following figures describe the interaction between the different layers.

Figure 5-1. USB Device Start-up and Stop

Figure 5-2. Management of Control Endpoint

Note: The udd_g_ctrlreq variable is used to communicate between UDD and UDC/UDIs.