4.1 Bluetooth® Low Energy LCC Timing

All timing operations in the Bluetooth® Low Energy LCC design are controlled internally by PIC32CX-BZ6. Hardware timers generate events that control when the DMA transfers data. Each time the DMA is done sending data, the Event System (EVSYS) is used to send an event to the Configurable Custom Logic (CCL) peripheral. The CCL will drive the Pixel Clock (PCLK) signal. The remaining timing signals VSYNC, HSYNC, and DEN are set by the CPU in GPIO mode. These signals are synchronized with the DMA. Changing the PCLK speed ultimately requires a change in DMA transfer speed, which is controlled by the timer speed.

The clock signals VSYNC, HSYNC, DEN, and PCLK are used to synchronize the pixel data with the LCD panel. The HSYNC signal tells the LCD panel when the data is at the start or end of a line. The VSYNC signal tells the LCD panel when the data is at the start or end of a frame. The DEN tells the panel when valid pixel data is being sent. The PCLK signal is the clock source for the whole system. One pulse updates the LCD, and the other signals must be synchronized with this clock.

The following figure highlights the timing signals for the initialization of the BLE LCC GUI. The PCLK signal (bottom signal) measurement is also highlighted in the image. This PCLK is the output of the CCL which was triggered by the DMA transfer. The top signal is the DEN signal, below the DEN is the HSYNC and above the PCLK signal is the VSYNC.