4.2 Bluetooth® Low Energy Parallel 8080 Timing

The timing operations for the external controller design are controlled within the external controller. The signals VSYNC, HSYNC, DEN, and PCLK are generated within the external controller. The PIC32CX-BZ6 interacts with the external controller using the parallel 8080 command signals Chip Select (CS), Read Data (RD), Write Enable (WE) , Register Select/Data Command (RSDC), RESET, and the eight data lines. For a full description of these signals, see the ILI9488 data sheet.

Instead of generating the timing signals directly, as seen in Bluetooth® Low Energy LCC, the MCU is responsible for transferring commands and data on the 8 data pins using the DMA and setting/clearing the parallel 8080 interface pins described above using GPIO. The Write Enable (WE) is generated in a similar fashion that the PCLK is generated in Bluetooth LE LCC. That is, a hardware timer generates events that trigger the DMA transfer. These events are transferred by the EVSYS to the CCL and the WR signal is generated. The WR signal tells the external controller when to latch the incoming data. The RSDC will determine if the incoming signal on the data lines are a command or data to be stored in the external controller.

The figure below highlights the timing signals for the initialization of the Bluetooth LE parallel 8080 GUI. The Write Enable (WR) signal (bottom signal) measurement is also highlighted in the image. The rising edge of the WR will latch the data inputs into the external controller. This signal is generated by the CCL on a DMA transfer. The RD signal (top signal) is active low, which will tell the external controller to output data. The RDSC signal (second signal) will be low when the incoming data is a command and high if the incoming data is real pixel data. Finally, the CS signal (third signal) will be low when the external controller is enabled.