2.3.5 Pulse-Width Modulation (PWM) Generator

The timer can be configured to generate a PWM signal when combined with a periodic ERS input signal. The timer rollover period must be greater than or equal to the ERS input period for correct operation. The PWM period is the period of the ERS input signal. The PWM duty cycle is determined by the PR value in the TUxyPR period register. The TUxyPR period register is also double-buffered to avoid glitches when changing the duty cycle. Use OM = Level mode to generate a PWM output. The OPOL bit controls whether the PWM signal is left-aligned or right-aligned.

The timer configuration settings are shown in Table 2-11.

Table 2-11. Timer Configuration
Timer Setting	Value
START	Rising ERS Edge
RESET	At Start + PR Match
STOP	At PR Match
CSYNC (Clock Sync)	Sync
ERS (Ext. Reset Source)	Periodic input of desired PWM frequency
OM (Output Mode)	Level mode
OPOL (Output Polarity)	Low when Idle (for left-aligned PWM) High when Idle (for right-aligned PWM)
PR (Period Register)	Calculated as per desired duty cycle and OPOL setting

When the periodic input rises (changes from 0 to 1), the timer is reset and starts counting. This process asserts the level output. The timer stops counting and resets at PR match, which deactivates the level output. This process repeats when the next rising input edge is detected. The level output generated is a PWM waveform. When OPOL = 0 (low when idle), the waveform is left-aligned PWM while, when OPOL = 1 (high when idle), the waveform is right-aligned PWM. A left-aligned PWM is shown in Figure 2-15 below.

The period of the PWM is dependent on the period of the ERS input signal:

P W M P e r i o d = E R S I n p u t P e r i o d

When OPOL = 0 (left-aligned PWM), the PR value determines the ON time. Hence, pulse width of the signal is:

P u l s e W i d t h = (P R v a l u e + 1) \times T U C L K p e r i o d

When OPOL = 1 (right-aligned PWM), the PR value determines the OFF time. Hence, pulse width of the signal is:

P u l s e W i d t h = P W M P e r i o d - ((P R v a l u e + 1) \times T U C L K p e r i o d)

The duty cycle ratio is a function of the pulse width and period of the PWM signal:

D u t y C y c l e R a t i o = \frac{P u l s e W i d t h}{P W M P e r i o d}

The resolution of the PWM is a function of the PWM period, UTMR rollover period, and UTMR size. The maximum PWM resolution is the size of the UTMR when the UTMR rollover period matches the PWM period.

P W M R e s o l u t i o n = ⌊ \log_{2} (\frac{P W M P e r i o d}{U T M R R o l l o v e r P e r i o d} \times 2^{U T M R S i z e}) ⌋ b i t s

Important: The UTMR rollover period must be greater than or equal to the ERS input period for proper PWM operation.

As an example, the following calculations show how to determine PR value and PWM resolution to generate a left-aligned 1 kHz PWM signal with 30% duty cycle. For this calculation, it is assumed that the UTMR clock, TUCLK = F_OSC = 16 MHz and UTMR size = 16 bits.

$P W M P e r i o d = E R S I n p u t P e r i o d = 1 / (1 k H z) = 1 m s$

$P u l s e W i d t h = Duty Cycle Ratio \times PWM Period = 30 % \times 1 m s = 300 μ s$

$P R v a l u e = \frac{P u l s e W i d t h}{T U C L K P e r i o d} - 1 = \frac{300 μ s}{1 / 16 M H z} - 1 = \frac{300 μ s}{62.5 n s} - 1 = 4799$

$P W M R e s o l u t i o n = ⌊ \log_{2} (\frac{1 m s}{4.096 m s} \times 2^{16}) ⌋ = 13 b i t s$