2.1.5 Interrupt-driven UART Implementation

The interrupt-driven UART driver has the same hardware requirement as the polled UART driver.

The basic functionality of the interrupt-driven implementation presented in this application note is to automate transmission and reception of larger chunks of data on the bus. This is done in two Interrupt Service Routines (ISRs). A set of helper functions can be called to set up all the necessary parameters, and these ISRs completes the transaction automatically. It is possible to do a Reset/Presence sequence or transfer anywhere between 1 and 255 bits of data in one direction without intervention.

To make the ISRs as simple as possible, they do not differentiate between transmission and reception. The UDRE ISR simply sends one bit from the data buffer every time it is run. The RXC ISR receives the same bit and puts it back into the data buffer no matter which direction data was sent. During transmission, the data sent will be identical to the data received, and the data buffer remains unchanged. During the reception, only ‘1’s should be transmitted, since the ‘write 1’ waveform is the same as the read waveform. The signal is sampled to find the value written by the slave device. This value is then placed in the data buffer.

Three global flags signal the state of the 1-Wire driver; busy, presence, and error. The busy flag is set as long as there is more data to transfer. The presence flag is set if a Presence signal is detected when sending a Reset signal. This flag remains set until a Reset signal on the bus does not return a Presence signal. The error flag is set when the UART receiver detects a frame error. In this situation, a new Reset signal should be transmitted on the bus. This will reset all slaves on the bus, as well as the internal state of UDRE and RXC ISRs.

As ISRs should be executed as quickly as possible, more complex functions like ROM commands are not implemented in the ISRs. The included example code shows how such behavior could be implemented in a Finite State Machine (FSM).