1.1 Transmit and Receive Buffers

The UART module contains dedicated transmit and receive buffers. The Transmit Enable Control (TXEN) bit enables/disables the transmitter, while the Receive Enable Control (RXEN) bit enables/disables the receiver.

The transmitter consists of the Transmit Shift Register (TSR) and one buffer register, UxTXB. Writes to UxTXB are transferred to the TSR when the TSR is empty. Bytes written to UxTXB while the TSR is full will be held in UxTXB until the TSR has completed shifting out its data. The Transmit Shift Register Empty Interrupt Flag (TXMTIF) bit can be used to determine if the TSR is empty, while the Transmit Buffer Empty Status (TXBE) bit and the UART Transmit Interrupt Flag (UxTXIF) bit indicate if the UxTXB is empty. Additionally, the Transmit Buffer Full Status (TXBF) bit can be used to indicate if the transmit buffer is full. If a new byte was written to UxTXB while the TXBF bit is set (TXBF = 1), the Transmit Write Error Status (TXWRE) bit becomes set and must be cleared in software to continue transmission. The TXBE bit can also be set by software to clear both the transmit buffer and the transmit shift register.

The receiver consists of the Receive Shift Register (RSR) and a two-level First-In First-Out (FIFO) buffer area. The buffer at the top of the FIFO, UxRXB, holds the first received byte (earliest byte to enter the FIFO). When a byte is received, it is loaded into the RSR, and if the receive FIFO is empty, the byte is transferred to UxRXB. If a second byte is received while the first byte remains in UxRXB, the second byte is transferred to the bottom of the FIFO. If a third byte is received, it is stored in the RSR until UxRXB is read. If any further bytes are received while the FIFO and RSR are full, the Receive FIFO Overflow Interrupt Flag (RXFOIF) bit becomes set, indicating a receive overflow condition.

In the event of an overflow, the Run During Overflow Control (RUNOVF) bit can be used to determine whether the RSR continues to receive data (after the overflow condition is cleared) or stop receiving data (legacy mode). An overflow condition can be cleared by reading UxRXB and clearing the RXFOIF bit, setting the RXBE bit, which flushes the entire FIFO, or by clearing the ON bit, which clears both the transmit and receive buffers and shift registers. When RUNOVF is set, the module will continue to synchronize the RSR with the incoming Start bits after the overflow condition has been cleared. It is important to note that although the FIFO will continue to operate in an overflow condition, the data will not be valid until the overflow condition has been cleared.

Transmit and receive polarity is user selectable. Both transmit and receive lines default to a logic ‘high’ Idle state. The Transmit Polarity Control (TXPOL) bit controls the transmit line polarity, while the Receive Polarity Control (RXPOL) bit controls the receive line polarity.