1.5 Stop Bits

The UART module offers a user-selectable number of Stop bits. The Stop bit selections are as follows:

• 1 Stop bit: UART transmits one Stop bit; the receiver verifies the first Stop bit received
• 1.5 Stop bits: UART transmits 1.5 Stop bits; the receiver verifies the first Stop bit only
• 2 Stop bits: UART transmits two Stop bits; the receiver verifies the first Stop bit only
• 2 Stop bits: UART transmits two Stop bits; the receiver verifies both

During normal operation, the transmitter returns to the Idle state for the number of Stop bit periods between each consecutively transmitted word. In all Stop bit configurations, the RX input is checked for an Idle condition during the middle of the first Stop bit period. In the case of the two Stop bit configuration where the receiver verifies both Stop bits, hardware checks the middle of both the first and second Stop bits for an Idle condition. If any Stop bit verification indicates a non-Idle condition, the Framing Error Interrupt Flag (FERIF) bit of the UART Error Interrupt Flag (UxERRIR) register becomes set, indicating a frame error for that particular byte.