1.3 Address Mode

The Asynchronous 9-bit UART Address mode allows the UART to communicate with multiple receivers sharing the same transmission line.

When transmitting in Address mode, the address of the receiver of interest is loaded into the UART Parameter 1 Low (UxP1L) register. When the address is loaded into UxP1L, hardware sets the 9th bit, indicating to the receiver that the byte is an address. Data bytes are written to the UxTXB register, similarly to normal UART operation. It is important to note that writes to UxP1L take precedence over writes to UxTXB. If both registers are written while the TSR is busy, the next byte loaded into TSR will come from UxP1L.

When receiving in Address mode, no received data will be transferred into the FIFO until a valid address is received. When a character with the 9th bit set is received, the eight LSb’s are compared to the UART Parameter 2 Low (UxP2L) register. In receive Address mode, UxP2L holds the receiver address, while the UART Parameter 3 Low (UxP3L) register holds the address mask. If an address match occurs, the eight LSb’s are transferred into the FIFO, while the 9th bit is transferred into the Parity Error Interrupt Flag (PERIF) bit. In this case, when PERIF is set, the UART Receive Interrupt Flag (UxRXIF) is suppressed, and if the Direct Memory Access (DMA) module is using the UxRXIF as a trigger, DMA transfers will be suspended. This prevents the DMA from writing address information into memory.