6.4 100-lead Package Pinout

Table 6-2. 100-lead Package Pinout
LQFP Pin	VFBGA Ball	TFBGA Ball	Power Rail	I/O Type	Primary		Alternate		PIO Peripheral A		PIO Peripheral B		PIO Peripheral C		PIO Peripheral D		Reset State
LQFP Pin	VFBGA Ball	TFBGA Ball	Power Rail	I/O Type	Signal	Dir	Signal	Dir	Signal	Dir	Signal	Dir	Signal	Dir	Signal	Dir	Signal, Dir, PU, PD, HiZ, ST
72	D8	D8	VDDIO	GPIO_AD	PA0	I/O	WKUP0⁽¹⁾	I	PWMC0_PWMH0	O	TIOA0	I/O	A17	O	I2SC0_MCK	–	PIO, I, PU, ST
70	C10	C10	VDDIO	GPIO_AD	PA1	I/O	WKUP1⁽¹⁾	I	PWMC0_PWML0	O	TIOB0	I/O	A18	O	I2SC0_CK	–	PIO, I, PU, ST
66	D10	D10	VDDIO	GPIO	PA2	I/O	WKUP2⁽¹⁾	I	PWMC0_PWMH1	O	–	–	DATRG	I	–	–	PIO, I, PU, ST
64	F9	F9	VDDIO	GPIO_AD	PA3	I/O	PIODC0⁽²⁾	I	TWD0	I/O	LONCOL1	I	PCK2	O	–	–	PIO, I, PU, ST
55	H10	H10	VDDIO	GPIO	PA4	I/O	WKUP3/PIODC1⁽³⁾	I	TWCK0	O	TCLK0	I	UTXD1	O	–	–	PIO, I, PU, ST
52	H9	H9	VDDIO	GPIO_AD	PA5	I/O	WKUP4/PIODC2⁽³⁾	I	PWMC1_PWML3	O	ISI_D4	I	URXD1	I	–	–	PIO, I, PU, ST
24	J2	J2	VDDIO	CLOCK	PA7	I/O	XIN32⁽⁴⁾	I	–	–	PWMC0_PWMH3	–	–	–	–	–	PIO, HiZ
25	K2	K2	VDDIO	CLOCK	PA8	I/O	XOUT32⁽⁴⁾	O	PWMC1_PWMH3	O	AFE0_ADTRG	I	–	–	–	–	PIO, HiZ
54	J9	J9	VDDIO	GPIO_AD	PA9	I/O	WKUP6/PIODC3⁽³⁾	I	URXD0	I	ISI_D3	I	PWMC0_PWMFI0	I	–	–	PIO, I, PU, ST
46	K9	K9	VDDIO	GPIO_AD	PA10	I/O	PIODC4⁽²⁾	I	UTXD0	O	PWMC0_PWMEXTRG0	I	RD	I	–	–	PIO, I, PU, ST
44	J8	J8	VDDIO	GPIO_AD	PA11	I/O	WKUP7/PIODC5⁽³⁾	I	QCS	O	PWMC0_PWMH0	O	PWMC1_PWML0	O	–	–	PIO, I, PU, ST
48	K10	K10	VDDIO	GPIO_AD	PA12	I/O	PIODC6⁽²⁾	I	QIO1	I/O	PWMC0_PWMH1	O	PWMC1_PWMH0	O	–	–	PIO, I, PU, ST
27	G5	G5	VDDIO	GPIO_AD	PA13	I/O	PIODC7⁽²⁾	I	QIO0	I/O	PWMC0_PWMH2	O	PWMC1_PWML1	O	–	–	PIO, I, PU, ST
34	H6	H6	VDDIO	GPIO_CLK	PA14	I/O	WKUP8/PIODCEN1⁽³⁾	I	QSCK	O	PWMC0_PWMH3	O	PWMC1_PWMH1	O	–	–	PIO, I, PU, ST
33	J6	J6	VDDIO	GPIO_AD	PA15	I/O	–	I	D14	I/O	TIOA1	I/O	PWMC0_PWML3	O	I2SC0_WS	–	PIO, I, PU, ST
30	J5	J5	VDDIO	GPIO_AD	PA16	I/O	–	I	D15	I/O	TIOB1	I/O	PWMC0_PWML2	O	I2SC0_DI	–	PIO, I, PU, ST
16	G1	G1	VDDIO	GPIO_AD	PA17	I/O	AFE0_AD6⁽⁵⁾	I	QIO2	I/O	PCK1	O	PWMC0_PWMH3	O	–	–	PIO, I, PU, ST
15	G2	G2	VDDIO	GPIO_AD	PA18	I/O	AFE0_AD7⁽⁵⁾	I	PWMC1_PWMEXTRG1	I	PCK2	O	A14	O	–	–	PIO, I, PU, ST
14	F1	F1	VDDIO	GPIO_AD	PA19	I/O	AFE0_AD8/WKUP9⁽⁶⁾	I	–	–	PWMC0_PWML0	O	A15	O	I2SC1_MCK	–	PIO, I, PU, ST
13	F2	F2	VDDIO	GPIO_AD	PA20	I/O	AFE0_AD9/WKUP10⁽⁶⁾	I	–	–	PWMC0_PWML1	O	A16	O	I2SC1_CK	–	PIO, I, PU, ST
21	J1	J1	VDDIO	GPIO_AD	PA21	I/O	AFE0_AD1/ PIODCEN2⁽⁸⁾	I	RXD1	I	PCK1	O	PWMC1_PWMFI0	I	–	–	PIO, I, PU, ST
26	J3	J3	VDDIO	GPIO_AD	PA22	I/O	PIODCCLK⁽²⁾	I	RK	I/O	PWMC0_PWMEXTRG1	I	NCS2	O	–	–	PIO, I, PU, ST
31	K5	K5	VDDIO	GPIO_AD	PA23	I/O	–	–	SCK1	I/O	PWMC0_PWMH0	O	A19	O	PWMC1_PWML2	O	PIO, I, PU, ST
38	K7	K7	VDDIO	GPIO_AD	PA24	I/O	–	–	RTS1	O	PWMC0_PWMH1	O	A20	O	ISI_PCK	I	PIO, I, PU, ST
40	H7	H7	VDDIO	GPIO_AD	PA25	I/O	–	–	CTS1	I	PWMC0_PWMH2	O	A23	O	MCCK	O	PIO, I, PU, ST
42	K8	K8	VDDIO	GPIO	PA26	I/O	–	–	DCD1	I	TIOA2	O	MCDA2	I/O	PWMC1_PWMFI1	I	PIO, I, PU, ST
50	H8	H8	VDDIO	GPIO_AD	PA27	I/O	–	–	DTR1	O	TIOB2	I/O	MCDA3	I/O	ISI_D7		PIO, I, PU, ST
79	A9	A9	VDDIO	GPIO	PA28	I/O	–	–	DSR1	I	TCLK1	I	MCCDA	I/O	PWMC1_PWMFI2	I	PIO, I, PU, ST
82	C7	C7	VDDIO	GPIO	PA30	I/O	WKUP11⁽¹⁾	I	PWMC0_PWML2	O	PWMC1_PWMEXTRG0	I	MCDA0	I/O	I2SC0_D0	–	PIO, I, PU, ST
83	A7	A7	VDDIO	GPIO_AD	PA31	I/O	–	–	SPI0_NPCS1	I/O	PCK2	O	MCDA1	I/O	PWMC1_PWMH2	O	PIO, I, PU, ST
12	E1	E1	VDDIO	GPIO	PB0	I/O	AFE0_AD10/ RTCOUT0⁽⁷⁾	I	PWMC0_PWMH0	O	–	–	RXD0	I	TF	I/O	PIO, I, PU, ST
11	E2	E2	VDDIO	GPIO	PB1	I/O	AFE1_AD0/ RTCOUT1⁽⁷⁾	I	PWMC0_PWMH1	O	GTSUCOMP	O	TXD0	I/O	TK	I/O	PIO, I, PU, ST
17	H1	H1	VDDIO	GPIO	PB2	I/O	AFE0_AD5⁽⁵⁾	I	CANTX0–	O–	–	–	CTS0	I	SPI0_NPCS0	I/O	PIO, I, PU, ST
20	H2	H2	VDDIO	GPIO_AD	PB3	I/O	AFE0_AD2/WKUP12⁽⁶⁾	I	CANRX0–	I–	PCK2	O	RTS0	O	ISI_D2	I	PIO, I, PU, ST
74	B9	B9	VDDIO	GPIO_MLB	PB4	I/O	TDI⁽⁹⁾	I	TWD1	I/O	PWMC0_PWMH2	O	MLBCLK–	I–	TXD1	I/O	PIO, I, PD, ST
77	C8	C8	VDDIO	GPIO_MLB	PB5	I/O	TDO/TRACESWO/ WKUP13⁽⁹⁾	O	TWCK1	O	PWMC0_PWML0	O	MLBDAT–	I/O–	TD	O	O
57	G8	G8	VDDIO	GPIO	PB6	I/O	SWDIO/TMS⁽⁹⁾	I	–	–	–	–	–	–	–	–	PIO,I,ST
63	E9	E9	VDDIO	GPIO	PB7	I/O	SWCLK/TCK⁽⁹⁾	I	–	–	–	–	–	–	–	–	PIO,I,ST
98	A2	A2	VDDIOP	CLOCK	PB8	I/O	XOUT⁽¹⁰⁾	O	–	–	–	–	–	–	–	–	PIO, HiZ
99	A1	A1	VDDIOP	CLOCK	PB9	I/O	XIN⁽¹⁰⁾	I	–	–	–	–	–	–	–	–	PIO, HiZ
61	F8	F8	VDDIO	GPIO	PB12	I/O	ERASE⁽⁹⁾	I	PWMC0_PWML1	O	GTSUCOMP	O	–	–	PCK0	O	PIO, I, PD, ST
100	B2	B2	VDDIO	GPIO_AD	PB13	I/O	DAC0⁽¹¹⁾	O	PWMC0_PWML2	O	PCK0	O	SCK0	I/O	–	–	PIO, I, PU, ST
1	B1	C1	VDDIO	GPIO_AD	PD0	I/O	DAC1⁽¹¹⁾	I	GTXCK	I	PWMC1_PWML0	O	SPI1_NPCS1		DCD0	I	PIO, I, PU, ST
92	D3	D2	VDDIO	GPIO	PD1	I/O	–	–	GTXEN	O	PWMC1_PWMH0	O	SPI1_NPCS2	I/O	DTR0	O	PIO, I, PU, ST
91	E3	E3	VDDIO	GPIO	PD2	I/O	–	–	GTX0	O	PWMC1_PWML1	O	SPI1_NPCS3	I/O	DSR0	I	PIO, I, PU, ST
89	B5	B5	VDDIO	GPIO	PD3	I/O	–	–	GTX1	O	PWMC1_PWMH1	O	UTXD4	O	RI0	I	PIO, I, PU, ST
88	A5	A5	VDDIO	GPIO_CLK	PD4	I/O	–	–	GRXDV	I	PWMC1_PWML2	O	TRACED0	O	DCD2	I	PIO, I, PU, ST
87	D5	D5	VDDIO	GPIO_CLK	PD5	I/O	–	–	GRX0	I	PWMC1_PWMH2	O	TRACED1	O	DTR2	O	PIO, I, PU, ST
85	B6	B6	VDDIO	GPIO_CLK	PD6	I/O	–	–	GRX1	I	PWMC1_PWML3	O	TRACED2	O	DSR2	I	PIO, I, PU, ST
84	A8	A6	VDDIO	GPIO_CLK	PD7	I/O	–	–	GRXER	I	PWMC1_PWMH3	O	TRACED3	O	RI2	I	PIO, I, PU, ST
80	B7	B7	VDDIO	GPIO_CLK	PD8	I/O	–	–	GMDC	O	PWMC0_PWMFI1	I	–	–	TRACECLK	O	PIO, I, PU, ST
78	B8	B8	VDDIO	GPIO_CLK	PD9	I/O	–	–	GMDIO	I/O	PWMC0_PWMFI2		AFE1_ADTRG	I	–	O	PIO, I, PU, ST
71	C9	C9	VDDIO	GPIO_MLB	PD10	I/O	–	–	GCRS	I	PWMC0_PWML0	O	TD	O	MLBSIG–	I/O–	PIO, I, PD, ST
69	D9	D9	VDDIO	GPIO_AD	PD11	I/O	–	–	GRX2	I	PWMC0_PWMH0	O	GTSUCOMP	O	ISI_D5	I	PIO, I, PU, ST
65	E10	E10	VDDIO	GPIO_AD	PD12	I/O	–	–	GRX3	I	CANTX1–	O–	SPI0_NPCS2	O	ISI_D6	I	PIO, I, PU, ST
62	E8	E8	VDDIO	GPIO_AD	PD13	I/O	–	–	GCOL	I	–	–	–	O	–	–	PIO, I, PU, ST
59	F10	F10	VDDIO	GPIO_AD	PD14	I/O	–	–	GRXCK	I	–	–	–	O	–	–	PIO, I, PU, ST
75	B10	B10	VDDIO	GPIO_AD	PD15	I/O	–	–	GTX2	O	RXD2	I	NWR1/NBS1	O	–	–	PIO, I, PU, ST
56	G9	G9	VDDIO	GPIO_AD	PD16	I/O	–	–	GTX3	O	TXD2	I/O	–	O	–	–	PIO, I, PU, ST
53	J10	J10	VDDIO	GPIO_AD	PD17	I/O	–	–	GTXER		SCK2	I/O	–	O	–	–	PIO, I, PU, ST
49	K6	K6	VDDIO	GPIO_AD	PD18	I/O	–	–	NCS1	O	RTS2	O	URXD4	I	–	–	PIO, I, PU, ST
47	K4	K4	VDDIO	GPIO_AD	PD19	I/O	–	–	NCS3	O	CTS2	I	UTXD4	O	–	–	PIO, I, PU, ST
45	K3	K3	VDDIO	GPIO	PD20	I/O	–	–	PWMC0_PWMH0	O	SPI0_MISO	I/O	GTSUCOMP	O	–	–	PIO, I, PU, ST
43	H5	H5	VDDIO	GPIO_AD	PD21	I/O	–	–	PWMC0_PWMH1	O	SPI0_MOSI	I/O	TIOA11	I/O	ISI_D1	I	PIO, I, PU, ST
41	J4	J4	VDDIO	GPIO_AD	PD22	I/O	–	–	PWMC0_PWMH2	O	SPI0_SPCK	O	TIOB11	I/O	ISI_D0	I	PIO, I, PU, ST
37	G4	G4	VDDIO	GPIO_AD	PD24	I/O	–	–	PWMC0_PWML0	O	RF	I/O	TCLK11	I	ISI_HSYNC	I	PIO, I, PU, ST
35	H3	H3	VDDIO	GPIO_AD	PD25	I/O	–	–	PWMC0_PWML1	O	SPI0_NPCS1	I/O	URXD2	I	ISI_VSYNC	I	PIO, I, PU, ST
36	G3	G3	VDDIO	GPIO	PD26	I/O	–	–	PWMC0_PWML2	O	TD	O	UTXD2	O	UTXD1	O	PIO, I, PU, ST
32	H4	H4	VDDIO	GPIO_AD	PD27	I/O	–	–	PWMC0_PWML3	O	SPI0_NPCS3	O	TWD2	O	ISI_D8	I	PIO, I, PU, ST
51	J7	J7	VDDIO	GPIO_AD	PD28	I/O	WKUP5⁽¹⁾		URXD3	I	CANRX1	I–	TWCK2	O	ISI_D9	I	PIO, I, PU, ST
23	K1	K1	VDDIO	GPIO_AD	PD30	I/O	AFE0_AD0⁽⁵⁾	I	UTXD3	0	–	–	–	–	ISI_D10	I	PIO, I, PU, ST
2	C1	B1	VDDIO	GPIO_AD	PD31	I/O	–	–	QIO3	I/O	UTXD3	O	PCK2	O	ISI_D11	I	PIO, I, PU, ST
4	C3	C3	VDDOUT	Power	VDDOUT	I	–	–	–	–	–	–	–	–	–	–	–
5	C2	C2	VDDIN	Power	VDDIN	I	–	–	–	–	–	–	–	–	–	–	–
6	D2	D3	GND	Ground	VREFN	I	–	–	–	–	–	–	–	–	–	–	–
9	D1	D1	VDDIO	Power	VREFP	I	–	–	–	–	–	–	–	–	–	–	–
58	G10	G10	VDDIO	RST	NRST	I	–	–	–	–	–	–	–	–	–	–	PIO, I, PU
60	F7	F7	VDDIO	TEST	TST	I	–	–	–	–	–	–	–	–	–	–	I, PD
19, 28, 68, 81	C5, F3, G7	C5, F3, G7	VDDIO	Power	VDDIO	I	–	–	–	–	–	–	–	–	–	–	–
73	A10	A10	VDDIO	TEST	JTAGSEL	I	–	–	–	–	–	–	–	–	–	–	I, PD
18, 22, 39, 76	C6, D6, G6	C6, D6, G6	VDDCORE	Power	VDDCORE	I	–	–	–	–	–	–	–	–	–	–	–
86	D7	D7	VDDPLL	Power	VDDPLL	I	–	–	–	–	–	–	–	–	–	–	–
93	E5	E5	VDDUTMII	Power	VDDUTMII	I	–	–	–	–	–	–	–	–	–	–	–
94	A4	A4	VDDUTMII	USBHS	HSDM	I/O	–	–	–	–	–	–	–	–	–	–	–
95	B4	B4	VDDUTMII	USBHS	HSDP	I/O	–	–	–	–	–	–	–	–	–	–	–
3, 7, 8, 10, 29, 67	E7, F4, F5, F6	E7, F4, F5, F6	GND	Ground	GND	I	–	–	–	–	–	–	–	–	–	–	–
	D4	D4	GNDANA	Ground	GNDANA	I	–	–	–	–	–	–	–	–	–	–	–
	A6	A8	GNDUTMI	Ground	GNDUTMI	I	–	–	–	–	–	–	–	–	–	–	–
	C4	C4	GNDPLLUSB	Ground	GNDPLLUSB	I	–	–	–	–	–	–	–	–	–	–	–
	E6	E4	GNDPLL	Ground	GNDPLL	I	–	–	–	–	–	–	–	–	–	–	–
96	B3	B3	VDDUTMIC	Power	VDDUTMIC	I	–	–	–	–	–	–	–	–	–	–	–
97	A3	A3	–	VBG	VBG	I	–	–	–	–	–	–	–	–	–	–	–
90	E4	E6	VDDPLLUSB	Power	VDDPLLUSB	I	–	–	–	–	–	–	–	–	–	–	–

Note:

WKUPx can be used if the PIO Controller defines the I/O line as “input”.
To select this extra function, refer to the Parallel Capture Mode section in the “Parallel Input/Output Controller (PIO)” chapter.
PIODCEN1/PIODCx has priority over WKUPx. Refer to the Parallel Capture Mode section in the “PIO” chapter.
Refer to the Slow Clock Generator section in the “Supply Controller (SUPC)” chapter.
To select this extra function, refer to the I/O Lines section in the “External Bus Interface (EBI)” chapter. This selection is independent of the PIO line configuration. PIO lines must be configured according to required settings (PU or PD).
Analog input has priority over WKUPx pin. To select the analog input, refer to the I/O Lines section in the “EBI” chapter. WKUPx can be used if the PIO controller defines the I/O line as “input”.
Analog input has priority over RTCOUTx pin. To select the analog input, refer to the I/O Lines section in the “EBI” chapter. Refer to the Waveform Generation section in the “Real-Time Clock (RTC)” chapter to select RTCOUTx.
Analog input has priority over WKUPx pin. To select the analog input, refer to the I/O Lines section in the “EBI” chapter. To select PIODCEN2, refer to the Parallel Capture Mode in the “PIO” chapter.
Refer to the System I/O Configuration Register (CCFG_SYSIO) in the “Bus Matrix (MATRIX)” chapter.
Refer to the Main Crystal Oscillator section in the “Clock Generator” chapter. This selection is independent of the PIO line configuration. PIO lines must be configured according to XINxx (I) and XOUTxx (O).
DAC0 is selected when DACC_CHER.CH0 is set. DAC1 is selected when DACC_CHER.CH1 is set. Refer to the DACC Channel Enable Register in the “Digital-to-Analog Converter Controller (DACC)” chapter.