4.1 Safety Mechanisms Grouped by Technique References

The provided safety mechanisms grouped under the ISO 26262-5:2018 technique references are provided below.

Table 4-1. Analog and Digital I/O (ISO 26262-5:2018, Table D.5)
Safety Mechanism	ISO26262-5:2018 Technique Reference	Diagnostic Coverage	Safety Mechanism	Safety Measure
Failure detection (1) by online monitoring	D.2.1.1	Low	SoC online monitoring of the device can be achieved by periodically reading the register map via SPI or I²C.	SPI or I²C
Failure detection (2) by online monitoring	D.2.1.1	Low	SoC online monitoring of the device can be achieved by periodically sensing the state of the GPIO pin or GPO pins.	GPIO, GPO
Test pattern	D.2.4.1	High	N/A	N/A
Code protection for digital I/O	D.2.4.2	Medium	N/A	N/A
Multichannel parallel output	D.2.4.3	High	N/A	N/A
Monitored outputs	D.2.4.4	High	Any internal status bit can be followed by the GPIO pin or GPO pins: System PLL loss-of-lock. Per-reference single-cycle monitor, precise frequency monitor, and other monitors. DPLL loss-of-lock, holdover, state, selected ref, and other status.	GPIO, GPO
Input comparison voting	D.2.4.5	High	N/A	N/A

Table 4-2. Communication Bus Serial/Parallel
Safety Mechanism	ISO 26262-5:2018 Technique Reference	Diagnostic Coverage	Safety Mechanism	Safety Measure
One-bit hardware redundancy	D.2.5.1	Low	N/A	N/A
Multi-bit hardware redundancy	D.2.5.2	Medium	N/A	N/A
Read back of sent message	D.2.5.9	Medium	Value previously written over SPI or I²C can be read back from the register map	SPI or I²C
Complete hardware redundancy	D.2.5.3	High	N/A	N/A
Inspection using test patterns	D.2.5.4	High	N/A	N/A
Transmission redundanc	D.2.5.5	Medium	N/A	N/A
Information redundancy	D.2.5.6	Medium	N/A	N/A
Frame counter	D.2.5.7	Medium	N/A	N/A
Timeout monitoring	D.2.5.8	Medium	N/A	N/A
Combination of information redundancy, frame counter, and timeout monitoring	D.2.5.6 D.2.5.7 D.2.5.8	High	N/A	N/A

Table 4-3. Program Sequence Monitoring/Clock (ISO 26262-5:2018, Table D.8)
Safety Mechanism	ISO 26262-5:2018 Technique Reference	Diagnostic Coverage	Safety Mechanism	Safety Measure
Watchdog with separate time base without time window	D.2.7.1	Low	N/A	N/A
Watchdog with separate time base and time window	D.2.7.2	Medium	N/A	N/A
Logical monitoring of program sequence	D.2.7.3	Medium	Use SPI or I²C access to read the current DPLL state periodically.	State Monitor
Combination of temporal and logical monitoring of program sequence	D.2.7.4	High	N/A	N/A
Combnation of temporal and logical monitoring of program sequences with time dependency	D.2.7.5	High	N/A	N/A

Table 4-4. Sensors (ISO 26262-5:2018, Table D.9)
Safety Mechanism	ISO 26262-5:2018 Technique Reference	Diagnostic Coverage	Safety Mechanism	Safety Measure
Failure detection by online monitoring	D.2.1.1	Low	N/A	N/A
Test pattern	D.2.4.1	High	N/A	N/A
Input comparison/ voting	D.2.4.5	High	N/A	N/A
Sensor valid range	D.2.8.1	Low	N/A	N/A
Sensor correlation	D.2.8.2	High	N/A	N/A
Sensor rationality check	D.2.8.3	Medium	N/A	N/A

Table 4-5. Non-volatile Memory (ISO 26262-5:2018, Table 32)
Safety Mechanism	ISO 26262-5:2018 Technique Reference	Diagnostic Coverage	Safety Mechanism	Safety Measure
Parity Bit	5.1.13.6	Low	N/A	N/A
Memory monitoring using error detection- correction codes	5.1.13.1	High	N/A	N/A
Modified checksum	5.1.13.2	Low	At power-up data in internal flash memory is loaded to RAM. A checksum is used to ensure the transfer is accurate.	Boot Status
Memory signature	5.1.13.3	High	N/A	N/A
Block replication	5.1.13.4	High	Internal flash memory can have two copies of all data.	Golden and Upgrade copies, Boot Golden command

DS20007165A

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