6.2.1 Failure of External Clock

For the system clock signal wired to the OSCI pin, the device is able to detect APLL loss of lock and create an alarm that the external clock has failed or is far off frequency.

For the reference input clock signals wired to the REF pins, the device is able to detect defects in the signal including clock period error (single-cycle monitor) and fractional frequency error (precise frequency monitor). The device can create an alarm that the reference input clock has failed.