4.1 ATA8510

Reception/transmission is realized in the Buffered mode. The maximum limit on the hardware data buffer (DFIFO) is 32 bytes; therefore, an additional Static Random Access Memory (SRAM) buffer with 282 bytes is created to realize the Z-Wave protocol.

Reception is realized in the Polling mode. For AL nodes, all three channels are polled sequentially. With given Z-Wave preamble length, it is possible to poll over all channels in a sufficient time without any loss of telegrams. FL nodes only poll over two channels because FL nodes do not use data rates up to 100 kbit/s.

The Flash software provides control and status registers, defined as global SRAM variables. For more details on the register structures, refer to Global SRAM Variables.

Received commands are decoded depending on the specification. To signalize a valid application frame reception to the host controller, the EVENT pin is set. This signalizes the host controller to decode the application frame via the Serial Peripheral Interface (SPI) read accesses to the SRAM variables. The host controller can initiate the application response frame via SPI write accesses to the SRAM variables.

To achieve TX data rate accuracy, an external Crystal Oscillator (XTO) frequency of 24.0 MHz fits best for all Z-Wave data rates.