32.4.14 I2C Bus Data Requirements

Table 32-22. 
Standard Operating Conditions (unless otherwise stated)
Param. No.Sym.CharacteristicMin.Max.UnitsConditions
SP100*THIGHClock high time100 kHz mode4.0—μsDevice must operate at a minimum of 1.5 MHz
400 kHz mode0.6—μsDevice must operate at a minimum of 10 MHz
SSP module1.5TCY—
SP101*TLOWClock low time100 kHz mode4.7—μsDevice must operate at a minimum of 1.5 MHz
400 kHz mode1.3—μsDevice must operate at a minimum of 10 MHz
SSP module1.5TCY—
SP102*TRSDA and SCL rise time100 kHz mode—1000ns
400 kHz mode20 + 0.1CB300nsCB is specified to be from 10-400 pF
SP103*TFSDA and SCL fall time100 kHz mode—250ns
400 kHz mode20 + 0.1CB250nsCB is specified to be from 10-400 pF
SP106*THD:DATData input hold time100 kHz mode0—ns
400 kHz mode00.9μs
SP107*TSU:DATData input setup time100 kHz mode250—nsNote 2
400 kHz mode100—ns
SP109*TAAOutput valid from clock100 kHz mode—3500nsNote 1
400 kHz mode——ns
SP110*TBUFBus free time100 kHz mode4.7—μsTime the bus must be free before a new transmission can start
400 kHz mode1.3—μs
SP111CBBus capacitive loading—400pF

* - These parameters are characterized but not tested.

Note:
  1. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
  2. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released.
Figure 32-20. I2C Bus Data Timing
Note: Refer to Figure 32-3 for load conditions.