18.9 Register Summary - Peripheral Pin Select Module
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
0x00 ... 0x1D8B | Reserved | |||||||||
| 0x1D8C | RA0PPS | 7:0 | RA0PPS[5:0] | |||||||
| 0x1D8D | RA1PPS | 7:0 | RA1PPS[5:0] | |||||||
| 0x1D8E | RA2PPS | 7:0 | RA2PPS[5:0] | |||||||
0x1D8F | Reserved | |||||||||
| 0x1D90 | RA4PPS | 7:0 | RA4PPS[5:0] | |||||||
| 0x1D91 | RA5PPS | 7:0 | RA5PPS[5:0] | |||||||
0x1D92 ... 0x1D97 | Reserved | |||||||||
| 0x1D98 | RB4PPS | 7:0 | RB4PPS[5:0] | |||||||
| 0x1D99 | RB5PPS | 7:0 | RB5PPS[5:0] | |||||||
| 0x1D9A | RB6PPS | 7:0 | RB6PPS[5:0] | |||||||
| 0x1D9B | RB7PPS | 7:0 | RB7PPS[5:0] | |||||||
| 0x1D9C | RC0PPS | 7:0 | RC0PPS[5:0] | |||||||
| 0x1D9D | RC1PPS | 7:0 | RC1PPS[5:0] | |||||||
| 0x1D9E | RC2PPS | 7:0 | RC2PPS[5:0] | |||||||
| 0x1D9F | RC3PPS | 7:0 | RC3PPS[5:0] | |||||||
| 0x1DA0 | RC4PPS | 7:0 | RC4PPS[5:0] | |||||||
| 0x1DA1 | RC5PPS | 7:0 | RC5PPS[5:0] | |||||||
| 0x1DA2 | RC6PPS | 7:0 | RC6PPS[5:0] | |||||||
| 0x1DA3 | RC7PPS | 7:0 | RC7PPS[5:0] | |||||||
0x1DA4 ... 0x1E0B | Reserved | |||||||||
| 0x1E0C | PPSLOCK | 7:0 | PPSLOCKED | |||||||
| 0x1E0D | INTPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E0E | T0CKIPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E0F | T1CKIPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E10 | T1GPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E11 | T3CKIPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E12 | T3GPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
0x1E13 ... 0x1E18 | Reserved | |||||||||
| 0x1E19 | T2INPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E1A | T4INPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
0x1E1B ... 0x1E1D | Reserved | |||||||||
| 0x1E1E | CCP1PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E1F | CCP2PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
0x1E20 ... 0x1E23 | Reserved | |||||||||
| 0x1E24 | PWMIN0PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E25 | PWMIN1PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E26 | PWM1ERSPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E27 | PWM2ERSPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
0x1E28 ... 0x1E38 | Reserved | |||||||||
| 0x1E39 | CWG1PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
0x1E3A ... 0x1E3C | Reserved | |||||||||
| 0x1E3D | CLCIN0PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E3E | CLCIN1PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E3F | CLCIN2PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E40 | CLCIN3PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E41 | CK1PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E42 | RX1PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E43 | CK2PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E44 | RX2PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
0x1E45 ... 0x1E46 | Reserved | |||||||||
| 0x1E47 | SSP1CLKPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E48 | SSP1DATPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E49 | SSP1SSPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E4A | SSP2CLKPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E4B | SSP2DATPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
| 0x1E4C | SSP2SSPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
0x1E4D ... 0x1E4F | Reserved | |||||||||
| 0x1E50 | ADACTPPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||
0x1E51 ... 0x1E52 | Reserved | |||||||||
| 0x1E53 | OPA1PPS | 7:0 | PORT[2:0] | PIN[2:0] | ||||||