30.12.2 Read Request

Name: READREQ
Offset: 0x02
Reset: 0x0000

Bit 15141312111098 
 RREQRCONT       
Access WR/W 
Reset 00 
Bit 76543210 
    ADDR[4:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bit 15 – RREQ Read Request

Writing a zero to this bit has no effect.

This bit will always read as zero.

Writing a one to this bit requests synchronization of the register pointed to by the Address bit group (READREQ. ADDR) and sets the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY).

Bit 14 – RCONT Read Continuously

When continuous synchronization is enabled, the register pointed to by the Address bit group (READREQ.ADDR) will be synchronized automatically every time the register is updated.

READREQ.RCONT prevents READREQ.RREQ from clearing automatically. For the continuous read mode, RREQ bit is required to be set once the RCONT bit is set.

Note: Once the continuous synchronization is enabled, the first write in the COUNT/CLOCK register will be stalled for a maximum of 6 APB + 6 TC clock cycles (the time for the on-going read synchronization to complete).
ValueDescription
0 Continuous synchronization is disabled.
1 Continuous synchronization is enabled.

Bits 4:0 – ADDR[4:0] Address

These bits select the offset of the register that needs read synchronization. In the TC, only COUNT and CCx are available for read synchronization.