16.6.2.6 Peripheral Clock Masking

It is possible to disable or enable the clock for a peripheral in the AHB or APBx clock domain by writing the corresponding bit in the Clock Mask register (APBxMASK) to zero or one. Refer to the table below for the default state of each of the peripheral clocks.

Table 16-1. Peripheral Clock Default State
Peripheral ClockDefault State
CLK_PAC0_APBEnabled
CLK_PM_APBEnabled
CLK_SYSCTRL_APBEnabled
CLK_GCLK_APBEnabled
CLK_WDT_APBEnabled
CLK_RTC_APBEnabled
CLK_EIC_APBEnabled
CLK_PAC1_APBEnabled
CLK_DSU_APBEnabled
CLK_NVMCTRL_APBEnabled
CLK_PORT_APBEnabled
CLK_HMATRIX_APBEnabled
CLK_PAC2_APBDisabled
CLK_SERCOMx_APBDisabled
CLK_TCx_APBDisabled
CLK_ADC_APBEnabled
CLK_ACx_APBDisabled
CLK_DAC_APBDisabled
CLK_PTC_APBDisabled
CLK_USB_APBEnabled
CLK_DMAC_APBEnabled
CLK_TCCx_APBDisabled
CLK_I2S_APBDisabled

When the APB clock for a module is not provided its registers cannot be read or written. The module can be re-enabled later by writing the corresponding mask bit to one.

A module may be connected to several clock domains (for instance, AHB and APB), in which case it will have several mask bits.

Note: Clocks should only be switched off if it is certain that the module will not be used. Switching off the clock for the NVM Controller (NVMCTRL) will cause a problem if the CPU needs to read from the flash memory. Switching off the clock to the Power Manager (PM), which contains the mask registers, or the corresponding APBx bridge, will make it impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset.