17.8.20 DPLL Status
| Name: | DPLLSTATUS |
| Offset: | 0x50 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIV | ENABLE | CLKRDY | LOCK | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 3 – DIV Divider Enable
| Value | Description |
|---|---|
| 0 | The reference clock divider is disabled |
| 1 | The reference clock divider is enabled |
Bit 2 – ENABLE DPLL Enable
| Value | Description |
|---|---|
| 0 | The DPLL is disabled |
| 1 | The DPLL is enabled |
Bit 1 – CLKRDY Output Clock Ready
| Value | Description |
|---|---|
| 0 | The DPLL output clock is off |
| 1 | The DPLL output clock is on |
Bit 0 – LOCK DPLL Lock Status
| Value | Description |
|---|---|
| 0 | The DPLL Lock signal is cleared |
| 1 | The DPLL Lock signal is asserted |