Operating Conditions
- 1.71V to 3.63V,
-40°C to +85°C, DC to 120 MHz
Core: Arm® Cortex®-M33 CPU running at up to 120 MHz
- 4 KB combined
instruction-cache and data-cache
- Nested Vector
Interrupt Controller (NVIC)
- Stack Limit
Checking
- Single Precision
Floating Point Unit (FPU)
- DSP
Instructions
- TrustZone® for
ARMv8-M (optional)
- Embedded Trace
Module (ETM) with Instrumentation Trace Macrocell (ITM)
- Trace Port
Interface Unit (TPIU)
- 16 secure and 16
non-secure MPU regions
Memories
- 2 MB/1 MB/512 KB
Flash
- 128 KB of Boot
Flash Memory (BFM)
- 64 KB of
Configuration Flash Memory (CFM)
- Flash
Supports:
- Error
Correction Code (ECC)
- Dual bank
with Read-While-Write (RWW) support
- Write
protection
- In-band
error reporting for both read and write accesses
- 512 KB, 256 KB,
128 KB SRAM Main Memory
- 32 KB or
Full SRAM can be retained in Standby mode and Hibernate
mode
- Up to 4 KB of
Tightly Coupled Memory (TCM)
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Security Features
- Hardware Security
Module (HSM)
- AES-128,
AES-192, and AES-256: Fully compliant with NIST FIPS
197
- ECB, CBC, CFB, OFB, CTR, GCM, CCM, XTS, CMAC
Modes
- Triple
DES support with up to 168-bit key length
- HASH/MAC
- SHA-1, SHA-256, SHA-224, SHA-384, SHA-512, and
SHA3 capability
- ChaCha20-Poly1305 Authenticated Encryption
- Key
Derivation Function (HKDF, KDF2…)
- Public
Key Cryptography: RSA, DSA, and ECC
- RSA with or without Chinese Remainder Theorem
(CRT). Up to 4096-bit key length
- RSA with/without Chinese Remainder Theorem (CRT).
Up to 4096-bit key length
- Prime Field P-192, P-224, P-256, P-384,
P-521
- Binary Field K-163, K-233, K-283, K-409,
K-571
- Binary Field B-163, B-233, B-283, B-409,
B-571
- P-224, P-256, P-384, and P-521 Elliptic Curve –
ECDSA Sign/Verify
- DSA support up to 2048-bit key length
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Security Features (continued...)
- Secure Flash
- Four 4
KBytes of secure pages
- Optimized
for secrets storage
- Data
Scrambling with user-defined key (optional)
- TrustZone for
flexible hardware isolation of memories and peripherals
(optional)
- Up to
four regions for the Flash
- Up to two
regions for the SRAM
- Individual security attribution for each peripheral,
I/O, external interrupt line, and Event System
Channel
- Up to
three debug access levels
- TrustRAM
- Address
and Data scrambling with user-defined key
- Chip-level tamper detection on physical RAM to resist
microprobing attacks
- Rapid
Tamper Erase on scrambling key and RAM data
- Silent
access for side channel attack resistance
- Data
remanence prevention
System
- Integrated
Power-on Reset (POR) and programmable Brown-out Reset
(BOR)
- Programmable
Low-Voltage Detect Module (LVD)
- 32-channel event
system for Inter-peripheral Core-independent Operation
- CRC-32
generator
Advanced Analog Features and Touch
- 12-bit ADC
module:
- 2 Msps
with up to 13 external channels and two internal
channels
- Single
and differential inputs
- External
reference support
- Temperature sensor with +-10°C accuracy
- Two analog
Comparators with window compare function
- 16x16 panel
Peripheral Touch controller (PTC)
- Supports
large self-capacitor sensor
- Support
external compensation and integration capacitors
Input/Output
- High current pins with up to 20 mA source/sink
- Up to 107 programmable I/O lines
- 16 external interrupts (EIC)
- One non-maskable interrupt (NMI)
- One Configurable Custom Logic (CCL) that supports:
- Combinatorial logic functions, such as AND, NAND, OR,
and NOR
- Sequential logic functions, such as Flip-Flop and
Latches
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High-Performance Peripherals
- Two DMA
instances:
- One
8-channels instance, and one 4-channels instance
respectively
- Up to
16-words internal FIFO per channel
- 4
different block transfer modes affecting the bus
transfer protocol and speed
- Built-in
CRC
- Assignable channel priority level (up to 4)
- Software or hardware DMA triggers
- Linked list Descriptor Control support
- Optional timestamp
- Word/half-word/byte transfer supported
- Event in/out support
- Up to two Secure
Digital Host Controller (SDHC) Interfaces
- Up to 50
MHz operation
- 4-bit or
1-bit interface
- Compatibility with SD and SDHC memory card
specification version 3.01
- Compatibility with SDIO specification version 3.0
- Compliant
with JDEC specification, MMC memory cards V4.51
- One Ethernet MAC
- 10/100
Mbps in MII and RMII with dedicated DMA
- IEEE®
1588 Precision Time Protocol (PTP) support
- IEEE 1588
Time Stamping Unit (TSU) support
- IEEE
802.3AZ energy efficiency support
- Support
for 802.1AS and 1588 precision clock synchronization
protocol
- Wake on
LAN support
- One 16-bit
External Bus Interface
- Supports
SRAM, NOR,NAND Flash with on the fly scrambling
- 8-bit or
16-bit data bus
- Up to 256
MB memory
- One Full-Speed
(12 Mbps) Universal Serial Bus (USB) 2.0 interface
- Embedded
host and device function
- Eight
endpoints
- On-chip
transceiver with integrated serial resistor
- Support
crystal-less operation in device mode
- One
USB2.0-compliant High-Speed controller
- Eight
endpoints with 9 KB of dedicated SRAM
- Low-speed, full-speed and high-speed support
- Low-power
mode (LPM) support
- Parallel Capture
Controller (PCC)
- Up to
14-bit parallel capture mode
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Power Management
- Idle mode for
fast wake up time
- Standby mode
- Hibernate mode up
to full RAM retention
- SleepWalking
Peripherals
Timers/Output Compare/Input Capture
- Four 32-bit
Timer/Counters for Control (TCC) with extended functions:
- With 6
compare/capture channels
- Double
buffered compare/capture channel
- Dead-time
Insertion
- Four 16-bit
Timer/Counters for Control (TCC) with extended functions:
- With 2
compare/capture channels
- Double-buffered compare/capture channel
- Dead-time
Insertion
- 32-bit Real-Time
Counter (RTC) with clock/calendar functions
- Watchdog Timer
(WDT) with Window mode
Debugger Development Support
- In-circuit and
in-application programming/debugging with SWD and JTAG
- Cortex®-M debugger port
- Supports 8
breakpoints and 4 watch points
- IEEE®1149-compatible (JTAG) boundary scan
- Non-intrusive
hardware-based instruction trace, Secure Debugging
Software and Tools Support: Develop Prototypes Quickly with A
Powerful, Easy-to-Use Ecosystem
- Get code off to a head start with MPLAB Code Configurator
- Graphically configure peripherals, software libraries, and
supported RTOS with MPLAB Harmony v3
- Download MPLAB XC Compiler
- Take advantage of MPLAB X IDE’s support for 32-bit MCUs
- Select the best debugger for the project: MPLAB ICE, ICD, or
PICkit™
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Communication Interfaces /Digital Peripherals
- Two CANFD
modules
- Support
CAN 2.0 A/B
- CAN FD
ISO 11898-1:2015
- Up to 8 Serial
Communication Interfaces (SERCOM), each configurable to operate
as:
- USART with full-duplex and single wire half-duplex
configuration
- I2C up to 3.4 MHz
- SPI (up
to 48 MHz)
- ISO7816 T = 0 or T = 1 protocols
- LIN Host/Client
- SQI configurable as additional SPI module (up to 80 MHz)
- Position Decoder (PDEC)
- Modes: QDEC, HALL, COUNTER
- One Inter-IC Sound Interface (SPI_IXS)
- 3-wire SPITM (supports all 4 SPI modes)
- 4-wire Framed SPI modes
- Audio Codec Protocols (I2S, Left/Right
Justified and PCM/DSP, I8s, Am824
- 4x32-bit, 8x16-bit or 16x8-bit FIFO
- 2
modules support 32 MHz SCK
- Modulation for MEMS Microphone
Clock Management
- 4 MHz to 48 MHz
Crystal Oscillator (XOSC)
- Clock
failure detection with safe clock switch
- 32.768 kHz ultra
low-power crystal oscillator (XOSC32K)
- Clock
failure detection with safe clock switch
- 32.768 kHz ultra
low-power internal RC oscillator (OSCULP32K)
- 48 MHz digital
Phase-Locked Loop (DFLL48M)
- 1.6 GHz Phase
Locked Loop (PLL1G6)
- Frequency
meter
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