56 Revision History

Revision C - April 2024


Section	Description
General	Minor changes of format. VREFP0 changed by VREFH SPIxC- TRL changed by SPIxCTRL VDDF changed by VDDFLASH ADC0 changed by ADC ADCn changed by ADC INSELx changed by INSELy Remove VBAT references
Features	Updated info of USB2.0 and Advanced Analog Features and Touch. Removed NIST compliant information.
1 Configuration Summary	Updated Brown-out Detection info in: Table 1-1 Table 1-2
2 Guidelines for Getting Started	Replaced Pie-Filters by Pi-Filters in the EMI/EMC/EFT (IEC61000-4-4 and IEC 61000-4-2) Suppression Considerations section
5 Package and Pinout	Updated MISC column in: Table 5-2 Table 5-3 Table 5-4
6 Signal Description	Added info of 64-Pin and 100-Pin in all the tables
7 Power Supplies and Startup Considerations	Removed VBAT in Figure 7-1
8 Product Mapping	Removed Base Address in: Table 8-5 Table 8-6 Table 8-7 Table 8-8
9 Peripherals	Updated Figure 9-1
10 Processor and Architecture	Modified format of Table 10-1 and added note
11 Memories	0x0054 is Reserved in Table 11-3 Updated 11.5.1.8 FUCFG5 - User Configuration Register 5 – Reserved
13 Cortex-M Cache Controller (CMCC)	Updated table in Peripheral Dependencies section Updated reference section in 13.5.7 Tightly Coupled Memory section Minor changes in 13.5.8.1 Cache Invalidate by Line Operation section Minor changes in 13.5.9 Cache Performance Monitoring section
15 Peripheral Access Controller (PAC)	Updated table in 15.4 Peripheral Dependencies section Removed bullet in the Register Access Protection section
16 Device Service Unit (DSU)	Updated 16.2 Features section Added notes in 16.4 Signal Description section Updated table in 16.5 Peripheral Dependencies section Updated first paragraph in 16.7.2.1 Cold Plugging Removed reference in 16.7.4 Boot Communication Channels section
17 Clock Distribution System	Updated Figure 17-1 Minor changes in 17.3.1 Overview section
18 Oscillator Controller (OSCCTRL)	Updated table in 18.5 Peripheral Dependencies section Replaced XOSCCTRLB[3] by XOSCCTRLB.GBW[1:0] and XOSCCTRLB[1:0] by XOSCCTRLB.GMAN[1:0] in 18.6.2 External Multipurpose Crystal Oscillator (XOSC) Operation section Replaced DFLL48M Loose Lock by DFLL48M Lose Lock After Wake and added note in 18.6.4.2 Additional DFLL48M Features section Added note in XOSCFAIL bitfield in the STATUS Register Added note in BWSEL bitfield in the PLL0CTRL Register Added note in POSTDIVn bitfield in the PLL0POSTDIVA Register
19 Generic Clock Controller (GCLK)	Updated Generic Clock Generators to 12 and updated Peripheral Channels to 48 Updated the Peripheral Clock Added 19.6.3.1 Enabling a Peripheral Clock Added note 5 in the 19.6.3.3 Selecting the Clock Source for a Peripheral section Updated GENCTRLn Register Updated PCHCTRLm Register
20 Main Clock (MCLK)	Updated Figure 20-2
21 32 KHz Oscillators Controller (OSC32KCTRL)	Updated bits of XOSC32K.STARTUP in 21.6.2 32 kHz External Crystal Oscillator (XOSC32K) Operation section
23 Frequency Meter (FREQM)	Minor changes of format in 23.1 Overview and 23.7.1.3 Measurement sections Added notes in SWRST bitfield in the CTRLA Register Added note in REFNUM bitfield in the CFGA Register
24 Real-Time Counter (RTC)	Updated Figure 24-3 Minor changes in 24.6.8.4.2 Active Layer Protection section Added Important note in CTRLA Register
25 Direct Memory Access Controller (DMAC)	Updated channels of DMA Controller modules 0 and 1 Updated DMA Event/Trigger Mapping
26 Supply Controller (SUPC)	Updated 26.2 Features section Minor changes in 26.3 Block Diagram section and removed VBAT in Figure 26-1 Updated table in 26.5 Peripheral Dependencies section Removed Battery Backup Power Switch section Added note in LVHIB bitfield in the VREGCTRL Register Added note in LPHIB and LPSTDBY bitfields in the VREFCTRL Register
27 Power Manager (PM)	Updated VREGSW in Table 27-3 Updated the Standby Mode section Updated the Hibernate and Backup Modes section Removed a sentence in 27.5.4.4 I/O Line State Retention in Hibernate and Backup Modes section
28 Reset Controller (RSTC)	Removed VBAT reference in 28.2 Features and the Reset Causes and Effects sections
29 External Interrupt Controller (EIC)	Replaced EXTINTx by EIC_EXTINTx in Figure 29-1 Minor changes in 29.6.1.1 Initialization section Added note in NMIFLAG Register
32 Event System (EVSYS)	Minor changes in 32.7.2.6 Edge Detection section Added Important note in PATH bitfield in CHANNELn Register
34 Serial Communication Interface (SERCOM)	Minor changes of format in 34.5.2.3 Clock Generation – Baud-Rate Generator section Updated 34.6.4.3.13 FIFO Operation section
35 Serial Quad Interface (SQI)	Updated Chip Selects to 4 Updated Figure 35-1 Updated CSEN bitfield in CFG Register
36 Universal Serial Bus Hi-Speed (USBHS)	Minor changes of format in 36.1 Overview section Replaced UPLLFSEL by CTRLA.REFCLKSEL in 36.3 Block Diagram section Removed OTG in 36.4 Signal Description section
38 Controller Area Network (CAN)	Updated number of CAN in 38.2 Features section Updated note in 38.3 Block Diagram section Updated Table 38-1 Minor changes in the Clocks section
41 True Random Number Generator (TRNG)	Updated second paragraph in 41.1 Overview section Removed one bullet in 41.2 Features section
42 Configurable Custom Logic (CCL)	Removed Timer/Counter Inputs (TC) section Removed note in Timer/Counter for Control Application Inputs (TCC) section Updated INSELy bitfield in LUTCTRLn Register
43 Analog-to-Digital Converter (ADC)	Updated 43.1 Overview section Updated 43.2 Features section Removed note in 43.3 Block Diagram section Removed note 3 in 43.4 Signal Description section Added Important note in 43.6.2.4 Conversion Timing and Sampling Rate section Updated 43.6.2.10 Initialization section Updated 43.6.7 Interrupts section Updated 43.6.8 Events section Updated SWCNVEN, SAMP and RQCNVRT bitfields in CTRLB Register Removed VBAT reference in ADCHSEL bitfield in CTRLB Register Bits 14 and 30 as reserved in CONFIG[0].CHNCFG1 Register Updated LVLk and CHNCMPEk bitfields in CONFIG[0].CHNCFG1 Register Updated FRACk and CSSk bitfields in CONFIG[0].CHNCFG2 Register Updated note 5 of TRGSRCk bitfield in CONFIG[0].CHNCFG4 and CONFIG[0].CHNCFG5 Registers
44 Analog Comparators (AC)	Updated MUXPOS bitfield in COMPCTRL0 Register
45 Position Decoder (PDEC)	Minor changes in 45.6.2.6.2 Secure Decoder Detection section Updated 45.6.3.4.1 Re-trigger Software Command or Event Action section Updated EVACT bitfield in EVCTRL Register
47 Timer/Counter for Control Applications (TCC)	Updated number of TCC in 47.1 Overview section Updated number of Compare/Capture Channels in 47.2 Features Updated values of table in the Feature Summary section Updated table in 47.4 Signal Description section Updated value of TCC bus clocks in the Clocks section Updated 47.6.1 Principle of Operation section Minor changes in 47.6.2.2 Initialization, 47.6.2.3 Enabling, Disabling, and Resetting, 47.6.2.4 Prescaler Selection, 47.6.2.5 Counter Operation and 47.6.3.2 Circular Buffer sections Removed last paragraph of Stop Command in 47.6.2.5 Counter Operation section Added note in Alternate RAMP2 (RAMP2A) Operation section Updated Table 47-4 Added Important note in 47.6.4.1 DMA Operation section Updated CPTEN bitfield in CTRLA Register Added note in DIR bitfield in CTRLBSET Updated CC bitfield in SYNCBUSY Register Updated CCBUFV and CMP bitfields in STATUS Register Updated CCy Register Updated CCBUFy Register
48 TrustRAM (TRAM)	Added note 4 in CTRLA Register Added note 2 in CTRLA Register
49 Peripheral Touch Controller (PTC)	Minor changes in 49.5.2 Clocks section
51 Electrical Characteristics	Updated Note 4

Revision B - May 2023


Section	Description
General	Updated DPLL to read PLL throughout the document
Features	Updated Advanced Analog Features and Touch instances with new data for channel numbers Reformatted the Communication Interfaces/Digital Peripherals section Updated the DMA instances
Configuration Summary	Replaced the existing tables with all new content
Signal Description	Replaced the existing tables with all new content
Block Diagram	Updated the Diagram with a new image
Pinout	Updated the following Pinout tables with all new content: 144-pin TQFP 100-pin TQFP 64-pin QFN and TQFP
Power Supplies and Startup Considerations	Updated the table in Power Supplies and Startup Considerations with new valued for the VDDREG Updated the bulleted items in Power Domain Constraints removing references to VDDCORE_USB1 and VDDUSB1 Updated the bulleted items in Power Supplies removing references to VDDUSB3V1 Renamed Boot ROM to Boot Flash (BFM) in Initial Instructions Fetching Updated VDDREG verbiage in Supply Order Updated I/O Pins with all new verbiage
10 Processor and Architecture	Removed the erroneous Overview section Updated NVIC Interrupt Line Mapping to remove ULDOOVHEAT and ULDORDY
Memories	Updated the Physical Memory Map Added s new section, PFM Error Correction Removed erroneous references to DAL and DAL-CFG in Configuration Flash Memory Removed an erroneous section pertaining to DAL Configuration Removed an erroneous section pertaining to CAL-OTP Configuration
CMCC	Updated the WAYNUM bitfield in the TYPE Register with a new table
IDAU	This chapter was completely rewritten in this revision
DSU	Corrected erroneous bitfield output for the CPUx bitfield in the DAL Register Removed an obsolete DATA Register Summary and associated Register
Clock Distribution System	Updated the Block Diagram with an all new image Updated the Diagram Example of a SERCOM_0 Clock to remove erroneous DPLL references
OSCCTRL	Removed erroneous clock references from the Block Diagram Updated Phase Locked Loop (PLL) Operation to remove erroneous Digital references Removed the following erroneous registers: DPLL1CTRL DPLL1FBDIV DPLL1REFDIV DPLL1POSTDIVA FRACDIV1 Added a new register, PLL0POSTDIVB
GCLK	Updated Figure 19-3 in Generic Clock Generator, changed DPLL to PLL and removed erroneous clock signals Corrected erroneous bitfield output in the following registers, and/or updated bitfield descriptions: SYNCBUSY GENCTRLn PCHCTRLm
MCLK	Added a new register, CLKDIV
OSC32KCTRL	Updated the CGM and STARTUP bitfields to properly display content in the XOSC32K Register
WDT	Updated the following registers to properly display bitfield information: EWCTRL
RTC	Updated the TAMPCTRL Register to properly display the INnACT bitfield output
SUPC	Removed erroneous LDO information from the Block Diagram Removed erroneous bitfields for ULDOOVHEAT, and ULDORDY from the following registers: INTENCLR INTENSET INTFLAG STATUS Removed erroneous bitfields for BKUP_VLD, SRAM_VLD, ULDOLEVEL, ULDSTDBY, ULDOEN, and OFFSTDBY from the VREGCTRL Register Added new information for the LVSTDBY and VREGOUT bitfields in the VREGCTRL Register
RSTC	Updated Reset Causes and Effects to remove an erroneous reference to BOD33
NVMCTRL	Replaced the image for the Block Diagram Updated Configuration Flash Memory to remove erroneous DALCFG, CAL, and SDAL references
ADC	Updated throughput rates for the ADC in Features Removed erroneous cores from the ADC block diagram, removed references to other modules from the ADC Trigger Block Diagram Updated the verbiage in the Signal Description to remove erroneous mentions to modules Updated the following registers with new naming conventions and/or verbiage updates to bitfields, including new notes and tables: CONFIG[0].CORCTRL CONFIG[0].CHNCFG1 CONFIG[0].CHNCFG2 CONFIG[0].CHNCFG3 CONFIG[0].CHNCFG5 CONFIG[0].CALCTRL EVCTRL0 FLTCTRL0 CORCHDATAID PFFDATA SYNCBUSY INTENCLR INTFLAG Added a new note to the CTRLC Register for the CNT bitfield
Electrical Specifications 85°C	Updated the typ specifications for Wake-Up Timing Updated FCLK_31 in Maximum Clock Frequencies Updated Xosc_3 and XOSC_5, and added XOSC_39 to External Oscillator (XOSC) Electrical Specifications Updated DFLL/PLL Electrical Specifications with new min, typ, and max specifications Updated the tables in Analog-to-Digital Converter (ADC) Electrical Specifications with new min, typ, and max specifications Replaced the tables in Comparator Electrical Specifications Updated Peripheral Touch Controller (PTC) Electrical Specifications with new max specifications Updated I²S Host Mode AC Electrical Specifications with a new max specification for I2S_33 Updated Timer Counter for Control Application (TCC) Electrical Specifications with a new max specification for TCC_15 Updated Non-Volatile Memory Controller (NVM) Electrical Specifications with a new min specification for NVM_3 Updated max specifications for SD_5 and SD_25 in SD/MMC Host Controller (SDHC) Electrical Specifications Updated min and max specifications in JTAG Electrical Specifications Updated SWD_1 max specifications in SWD 2-Wire Electrical Specifications
Extended Temperature Electrical Characterstics (125°C)	All new section
Schematic Checklist	Updated the voltage specifications in the Diagram in Introduction
Packaging	Updated the following packages with new images and/or new information: 64-pin TQFP 64 Lead VQFN 100 Lead TQFP 144 Lead TQFP

Revision A - November 2022

Terminology used in this document may not match with the contents of other Microchip documentation and collateral. For any questions or concerns regarding terminology, contact a Microchip support or sales representative.

This is the initial released version of this document.