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32-bit MCU with TrustZone and Integrated Security
Up to 2 MB Live-Update Flash and 512 KB SRAM with Hardware Security Module (HSM) for Secure Connectivity Applications
1 Configuration Summary
2 Guidelines for Getting Started
2.1 Basic Connection Requirements
2.2 Decoupling Capacitors
2.3 External Reset (RESET) Pin
2.4 Debugging or Programming Pins
2.5 JTAG
2.6 Trace
2.7 External Oscillator Pins
2.8 Unused I/Os
2.9 Considerations When Interfacing to Remotely Powered Circuits
2.10 Designing for High-Speed Peripherals
3 Ordering Information
4 Block Diagram
5 Package and Pinout
5.1 64-Pin Packages
5.2 100-Pin Packages
5.3 144-Pin Packages
6 Signal Description
7 Power Supplies and Startup Considerations
7.1 Power Domain Overview
7.2 Power Domain Constraints
7.3 Power Up
7.4 Power-on Reset and Brown-out Reset
7.5 Analog Peripherals Considerations
7.6 Device Startup
8 Product Mapping
8.1 Code Address Space
8.2 SRAM Address Space
8.3 Peripheral Address Space
8.4 External RAM Address Space
8.5 Peripheral Bus A Address Map
8.6 Peripheral Bus B Address Map
8.7 Peripheral Bus C Address Map
8.8 Peripheral Bus AHB Address Map
8.9 Flash CFM Configuration Address Map
9 Peripherals
9.1 Register Description
10 Processor and Architecture
10.1 Nested Vectored Interrupt Controller
10.2 High-Speed Bus
11 Memories
11.1 Embedded Memories
11.2 Physical Memory Map
11.3 SRAM Memory Configuration
11.4 PFM Error Correction
11.5 Configuration Flash Memory (CFM)
11.6 BFM Integrity Check
11.7 CAL OTP Configuration
11.8 Unique ID (UID)
12 Hardware Security Module (HSM)
12.1 Features
12.2 For More Information
13 Cortex-M Cache Controller (CMCC)
13.1 Overview
13.2 Features
13.3 Block Diagram
13.4 Peripheral Dependencies
13.5 Functional Description
13.6 DEBUG Mode
13.7 RAM Properties
13.8 Register Summary
14 Implementation Defined Attribution Unit (IDAU)
14.1 Overview
14.2 IDAU Region Types
14.3 Main Region Types
14.4 Splittable Main Regions
14.5 Exempt_B Layout
14.6 SECNNONSEC_B Layout
14.7 IDAU Regions IDS
14.8 IDAU Regions Configuration
14.9 Configuration Write Lock
14.10 Linked IDAU Regions
14.11 IDAU Register Summary
15 Peripheral Access Controller (PAC)
15.1 Overview
15.2 Features
15.3 Block Diagram
15.4 Peripheral Dependencies
15.5 Functional Description
15.6 Register Summary
16 Device Service Unit (DSU)
16.1 Overview
16.2 Features
16.3 PIC32CK SG/GC DSU Block Diagram
16.4 Signal Description
16.5 Peripheral Dependencies
16.6 Indexing
16.7 Debug Operation
16.8 Multi-Processor Support
16.9 Programming
16.10 Security Enforcement
16.11 Device Identification
16.12 Functional Description
16.13 Register Summary
16.14 DATA Register Summary in MBIST Mode
17 Clock Distribution System
17.1 Clock Distribution
17.2 Synchronous and Asynchronous Clocks
17.3 Register Synchronization
17.4 Enabling a Peripheral
17.5 On Demand Clock Requests
17.6 Power Consumption Versus Speed
17.7 Clocks after Reset
18 Oscillator Controller (OSCCTRL)
18.1 Overview
18.2 Features
18.3 OSCCTRL Block Diagram
18.4 Signal Descriptions
18.5 Peripheral Dependencies
18.6 Functional Description
18.7 Register Summary
19 Generic Clock Controller (GCLK)
19.1 Overview
19.2 Features
19.3 Block Diagram
19.4 Signal Description
19.5 Peripheral Dependencies
19.6 Functional Description
19.7 Register Summary
20 Main Clock (MCLK)
20.1 Overview
20.2 Features
20.3 Block Diagram
20.4 Peripheral Dependencies
20.5 Functional Description
20.6 Register Summary
21 32 KHz Oscillators Controller (OSC32KCTRL)
21.1 Overview
21.2 Features
21.3 Block Diagram
21.4 Signal Description
21.5 Peripheral Dependencies
21.6 Functional Description
21.7 Register Summary
22 Watchdog Timer (WDT)
22.1 Overview
22.2 Features
22.3 Block Diagram
22.4 Peripheral Dependencies
22.5 Functional Description
22.6 Register Summary
23 Frequency Meter (FREQM)
23.1 Overview
23.2 Features
23.3 Block Diagram
23.4 Signal Description
23.5 Peripheral Dependencies
23.6 Clocks
23.7 Functional Description
23.8 Register Summary
24 Real-Time Counter (RTC)
24.1 Overview
24.2 Features
24.3 Block Diagram
24.4 Signal Description
24.5 Peripheral Dependencies
24.6 Functional Description
24.7 Register Summary - 32-bit Counter Mode
24.8 Register Summary - 16-bit Counter Mode
24.9 Register Summary Clock/Calendar Mode
25 Direct Memory Access Controller (DMAC)
25.1 Overview
25.2 Features
25.3 Block Diagram
25.4 Peripheral Dependencies
25.5 Indexing
25.6 DMA Event/Trigger Mapping
25.7 Applications
25.8 Module Description
25.9 Register Summary
25.10 Channelk Register Summary, k = 0,1,...,11
26 Supply Controller (SUPC)
26.1 Overview
26.2 Features
26.3 Block Diagram
26.4 Signals Description
26.5 Peripheral Dependencies
26.6 Functional Description
26.7 Register Summary
27 Power Manager (PM)
27.1 Overview
27.2 Features
27.3 Block Diagram
27.4 Peripheral Dependencies
27.5 Functional Description
27.6 Register Summary
28 Reset Controller (RSTC)
28.1 Overview
28.2 Features
28.3 Block Diagram
28.4 Signals Description
28.5 Peripheral Dependencies
28.6 Functional Description
28.7 Register Summary
29 External Interrupt Controller (EIC)
29.1 Overview
29.2 Features
29.3 Block Diagram
29.4 Signal Description
29.5 Peripheral Dependencies
29.6 Functional Description
29.7 Register Summary
30 Non-Volatile Memory Controller (NVMCTRL)
30.1 Block Diagram
30.2 Flash Controller, Write
30.3 Flash Controller, Read
31 Ethernet Media Access Controller (ETH)
31.1 Overview
31.2 Features
31.3 Block Diagram
31.4 Signal Interface
31.5 Peripheral Dependencies
31.6 Functional Description
31.7 Programming Interface
31.8 Register Summary
32 Event System (EVSYS)
32.1 Overview
32.2 Features
32.3 Block Diagram
32.4 Peripheral Dependencies
32.5 Power Management
32.6 Clocks
32.7 Functional Description
32.8 Register Summary
33 I/O Pin Controller (PORT)
33.1 Overview
33.2 Features
33.3 Block Diagram
33.4 Signal Description
33.5 Peripheral Dependencies
33.6 I/O Lines
33.7 Clocks
33.8 CPU AHB Bus
33.9 Power Management
33.10 Debug Operation
33.11 Functional Description
33.12 Register Summary
34 Serial Communication Interface (SERCOM)
34.1 Overview
34.2 Features
34.3 Block Diagram
34.4 Peripheral Dependencies
34.5 Functional Description
34.6 SERCOM USART - SERCOM Synchronous and Asynchronous Receiver and Transmitter
34.7 SERCOM Serial Peripheral Interface (SPI)
34.8 SERCOM I2C
35 Serial Quad Interface (SQI)
35.1 Overview
35.2 Features
35.3 Block Diagram
35.4 Peripheral Dependencies
35.5 Functional Description
35.6 Register Summary
36 Universal Serial Bus Hi-Speed (USBHS)
36.1 Overview
36.2 Features
36.3 Block Diagram
36.4 Signal Description
36.5 Peripheral Dependencies
36.6 Functional Description
36.7 Register Summary: USB Common Registers
36.8 Register Summary: USB Endpoint0 Common Registers
36.9 Register Summary: USB Host Mode Only Registers
36.10 Register Summary: Home Mode Endpoint0 Registers
36.11 Register Summary: USB Host Mode Endpoint1-7 Registers
36.12 Register Summary: Device Mode Only Common Registers
36.13 Register Summary: Device Mode Endpoint0 Registers
36.14 Register Summary: Device Mode Endpoint1-7 Registers
37 Full-Speed Universal Serial Bus (USBFS)
37.1 Overview
37.2 Features
37.3 USB Block Diagram
37.4 Signal Description
37.5 Peripheral Dependencies
37.6 Functional Description
37.7 Communication Device Host Register Summary
37.8 Device Registers - Common -Register Summary
37.9 Device Endpoint Register Summary
37.10 Endpoint Descriptor Structure
37.11 Device Endpoint RAM Register Summary
37.12 Host Registers - Common - Register Summary
37.13 Host Registers - Pipe - Register Summary
37.14 Pipe Descriptor Structure
37.15 Host Registers - Pipe RAM - Register Summary
38 Controller Area Network (CAN)
38.1 Overview
38.2 Features
38.3 Block Diagram
38.4 Signal Description
38.5 Peripheral Dependencies
38.6 Functional Description
38.7 Register Summary
39 External Bus Interface (EBI)
39.1 Overview
39.2 Features
39.3 EBI Block Diagram
39.4 I/O Lines Description
39.5 Application Example
39.6 Peripheral Dependencies
39.7 Functional Description
39.8 Register Summary
40 SD/MMC Host Controller (SDHC)
40.1 Overview
40.2 Features
40.3 Block Diagram
40.4 Connection Diagram
40.5 Signal Description
40.6 Peripheral Dependencies
40.7 Functional Description
40.8 Register Summary
41 True Random Number Generator (TRNG)
41.1 Overview
41.2 Features
41.3 Block Diagram
41.4 Peripheral Dependencies
41.5 Clocks
41.6 Functional Description
41.7 Register Summary
42 Configurable Custom Logic (CCL)
42.1 Overview
42.2 Features
42.3 Block Diagram
42.4 Signal Description
42.5 Peripheral Dependencies
42.6 Functional Description
42.7 Register Summary
43 Analog-to-Digital Converter (ADC)
43.1 Overview
43.2 Features
43.3 Block Diagram
43.4 Signal Description
43.5 Peripheral Dependencies
43.6 Functional Description
43.7 Register Summary
44 Analog Comparators (AC)
44.1 Overview
44.2 Features
44.3 Block Diagram
44.4 Analog Connections
44.5 Peripheral Dependencies
44.6 Functional Description
44.7 Register Summary
45 Position Decoder (PDEC)
45.1 Overview
45.2 Features
45.3 Block Diagram
45.4 Signal Description
45.5 Peripheral Dependencies
45.6 Functional Description
45.7 Register Summary
46 Parallel Capture Controller (PCC)
46.1 Overview
46.2 Features
46.3 Block Diagram
46.4 Signal Description
46.5 Peripheral Dependencies
46.6 Functional Description
46.7 Register Summary
47 Timer/Counter for Control Applications (TCC)
47.1 Overview
47.2 Features
47.3 Block Diagram
47.4 Signal Description
47.5 Peripheral Dependencies
47.6 Functional Description
47.7 Register Summary
48 TrustRAM (TRAM)
48.1 Overview
48.2 Features
48.3 Block Diagram
48.4 Peripheral Dependencies
48.5 Functional Description
48.6 Register Summary
49 Peripheral Touch Controller (PTC)
49.1 Overview
49.2 Features
49.3 Block Diagram
49.4 Signal Description
49.5 Peripheral Dependencies
49.6 Functional Description
50 Inter-IC Sound Controller (I2S)
50.1 Overview
50.2 Features
50.3 Block Diagram
50.4 Peripheral Dependencies
50.5 Functional Description
50.6 Register Summary
51 Electrical Characteristics
51.1 Absolute Maximum Electrical Characteristics
51.2 CPU Electrical Characteristics
51.3 Power Supply
51.4 MCU Active Power
51.5 MCU Idle Power
51.6 MCU Standby Power
51.7 MCU Hibernate Power
51.8 MCU Backup Power
51.9 MCU OFF Power
51.10 Wake-Up Timing
51.11 Peripheral Active Power
51.12 I/O Pin Electrical Specifications
51.13 Internal Voltage Reference Electrical Specifications
51.14 Maximum Clock Frequencies
51.15 External Oscillator (XOSC) Electrical Specifications
51.16 External 32.768 kHz Oscillator (XOSC32) Electrical Specifications
51.17 Low Power Internal 32kHz RC Oscillator (OSCULP32K) Electrical Specifications
51.18 DFLL/PLL Electrical Specifications
51.19 Analog-to-Digital Converter (ADC) Electrical Specifications
51.20 Comparator Electrical Specifications
51.21 Peripheral Touch Controller (PTC) Electrical Specifications
51.22 Serial Peripheral Interface (SPI) Electrical Specifications
51.23 UART Electrical Specifications
51.24 I2S Electrical Specifications
51.25 I2C Electrical Specifications
51.26 SQI/QSPI Electrical Specifications
51.27 Controller Area Network (CAN) Electrical Specifications
51.28 Timer Counter for Control Applications (TCC) Electrical Specifications
51.29 Universal Serial Bus (USB) Electrical Specifications
51.30 Parallel Capture Controller (PCC) Electrical Specifications
51.31 Non-Volatile Memory Controller (NVM) Electrical Specifications
51.32 Ethernet MAC (ETH) Electrical Specifications
51.33 Frequency Meter (FREQM) Electrical Specifications
51.34 True Random Number Generator (TRNG) Electrical Specifications
51.35 Position Decoder (PDEC) Electrical Specifications
51.36 SD/MMC Host Controller (SDHC) Electrical Specifications
51.37 External Bus Interface (EBI) Electrical Specifications
51.38 JTAG Electrical Specifications
51.39 SWD 2-Wire Electrical Specifications
52 Packaging Information
52.1 Package Marking Information
52.2 Package Drawings
52.3 Soldering Profile
53 Schematic Checklist
53.1 Introduction
54 Common Conventions
54.1 Numerical Notation
54.2 Memory Size and Type
54.3 Frequency and Time
54.4 Registers and Bits
55 Acronyms and Abbreviations
56 Revision History
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