44.7.12 Comparator Control 0
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | COMPCTRL0 |
| Offset: | 0x34 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Enable Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SUT[5:0] | OUT[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FLEN[2:0] | HYST[1:0] | SPEED | SWAP | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MUXPOS[2:0] | MUXNEG[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RUNSTDBY | INTSEL[1:0] | SINGLE | ENABLE | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bits 31:26 – SUT[5:0] Start-up Time
Each time a comparator is enabled, the comparison will be enabled after the startup time specified by these bits using the formula:
SUT = (20us / ((2^PRESCALER) x t(GCLK_AC))).
Refer to electrical specifications for minimum analog comparator start-up time required to initialize COMPCTRLn.SUT bits to.
- If COMPCTRLn.SINGLE=1 even if comparator COMPCTRLn.ENABLE=1 the comparator is turned off to conserve power. When CTRLB.STARTn is set by the user to start the comparison the comparator is enabled, after COMPCTRLn.SUT time has expired the comparison is made and then the comparator is again shut off to conserve power ready for the next time.
- These bits can be written only while COMPCTRLn.ENABLE is zero.
- Zero value is not allowed and can lead to unpredictable behavior.
Bits 25:24 – OUT[1:0] Output
These bits configure the output selection for comparator n. COMPCTRLn.OUT can be written only while COMPCTRLn.ENABLE is zero.
| Value | Name | Description |
|---|---|---|
| 0x0 | OFF | The output of COMPn is not routed to the COMPn I/O port |
| 0x1 | ASYNC | The asynchronous output of COMPn is routed to the COMPn I/O port |
| 0x2 | SYNC | The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port |
Bits 23:21 – FLEN[2:0] Filter Length
These bits configure the filtering for comparator n. COMPCTRLn.FLEN can only be written while COMPCTRLn.ENABLE is zero.
| Value | Name | Description |
|---|---|---|
| 0x0 | OFF | No filtering (Not valid if COMPCTRLn.OUT = 0x2 = sync) |
| 0x1 | MAJ3 | 3-bit majority function (2 of 3) |
| 0x2 | MAJ5 | 5-bit majority function (3 of 5) |
| 0x3-0x7 | N/A | Reserved |
Bits 20:19 – HYST[1:0] Hysteresis Level
These bits indicate the hysteresis level of comparator n when hysteresis is enabled (COMPCTRLn.HYSTEN=1). Hysteresis is available only for continuous mode (COMPCTRLn.SINGLE=0). COMPCTRLn.HYST can be written only while COMPCTRLn.ENABLE is zero.
| Value | Name | Description |
|---|---|---|
| 0x0 | HYST10 | 10mV (Refer to AC Electrical Specifications) |
| 0x1 | HYST20 | 20mV (Refer to AC Electrical Specifications) |
| 0x2 | HYST40 | 40mV (Refer to AC Electrical Specifications) |
| 0x3 | HYST60 | 60mV (Refer to AC Electrical Specifications) |
Bit 17 – SPEED Speed Selection
This bit indicates the speed/propagation delay mode of comparator n. COMPCTRLn.SPEED can be written only while COMPCTRLn.ENABLE is zero.
| Value | Name | Description |
|---|---|---|
| 0x0 | HIGH | High speed, high power |
| 0x1 | LOW | Low speed, low power |
Bit 16 – SWAP Swap Inputs and Invert
This bit swaps the positive and negative inputs to COMPn and inverts the output. This function can be used for offset cancellation. COMPCTRLn.SWAP can be written only while COMPCTRLn.ENABLE is zero.
| Value | Description |
|---|---|
| 0 | The output of MUXPOS connects to the positive input, and the output of MUXNEG connects to the negative input. |
| 1 | The output of MUXNEG connects to the positive input, and the output of MUXPOS connects to the negative input. |
Bits 14:12 – MUXPOS[2:0] Positive Input Mux Selection
These bits select which input will be connected to the positive input of comparator n. COMPCTRLn.MUXPOS can be written only while COMPCTRLn.ENABLE is zero.
| Value | Name | Description |
|---|---|---|
| 0x0 | AC_AIN0 | Comparator(n) Positive analog input AIN0 |
| 0x1 | AC_AIN1 | Comparator(n) Positive analog input AIN1 |
| 0x2 | AC_AIN2 | Comparator(n) Positive analog input AIN2 |
| 0x3 | AC_AIN3 | Comparator(n) Positive analog input AIN3 |
| 0x4 | AVSS | Internal AVSS connection |
| 0x5 | Reserved | Reserved |
| 0x6 | Reserved | Reserved |
| 0x7 | INTDAC | Internal DACn |
Bits 10:8 – MUXNEG[2:0] Negative Input Mux Selection
These bits select which input will be connected to the negative input of comparator n. COMPCTRLn.MUXNEG can only be written while COMPCTRLn.ENABLE is zero.
| Value | Name | Description |
|---|---|---|
| 0x0 | AC_AIN0 | Comparator(n) Negative analog input AIN0 |
| 0x1 | AC_AIN1 | Comparator(n) Negative analog input AIN1 |
| 0x2 | AC_AIN2 | Comparator(n) Negative analog input AIN2 |
| 0x3 | AC_AIN3 | Comparator(n) Negative analog input AIN3 |
| 0x4 | AVSS | Internal AVSS connection |
| 0x5 | BANDGAP | Internal 0.8v Bandgap |
| 0x6 | AVSS | AVSS |
| 0x7 | INTDAC | Internal DACn |
Bit 6 – RUNSTDBY Run in Standby
This bit controls the behavior of the comparator during standby sleep mode. This bit can only be written while COMPCTRLn.ENABLE is zero.
| Value | Description |
|---|---|
| 0 | The comparator n is disabled during sleep. |
| 1 | The comparator n continues to operate during sleep. |
Bits 5:4 – INTSEL[1:0] Interrupt Selection
These bits select the condition for comparator n (n=0,1) to generate an interrupt or event. COMPCTRLn.INTSEL can be written only while COMPCTRLn.ENABLE is zero.
| Value | Name | Description |
|---|---|---|
| 0x0 | TOGGLE | Interrupt on comparator n output toggle |
| 0x1 | RISING | Interrupt on comparator n output rising |
| 0x2 | FALLING | Interrupt on comparator n output falling |
| 0x3 | EOC | Interrupt on end of comparison (single-shot mode only) |
Bit 3 – SINGLE Single-Shot Mode
This bit determines the operation of comparator n. COMPCTRLn.SINGLE can be written only while COMPCTRLn.ENABLE is zero.
When CTRLB.STARTn is set by the user to start the comparison the comparator is enabled, after COMPCTRLn.SUT time has expired the comparison is made and then the comparator is again shut off to conserve power ready for the next time.
| Value | Description |
|---|---|
| 0 | Comparator n operates in continuous measurement mode. |
| 1 | Comparator n operates in single-shot mode. |
Bit 1 – ENABLE Enable
Due to synchronization, there is delay from updating the register until the comparator is enabled/disabled. The value written to COMPCTRLn.ENABLE will read back immediately after being written. SYNCBUSY.COMPCTRLn is set. SYNCBUSY.COMPCTRLn is cleared when the peripheral is enabled/disabled.
Writing a one to COMPCTRLn.ENABLE will prevent further changes to the other bits in COMPCTRLn. These bits remain protected until COMPCTRLn.ENABLE is written to zero and the write is synchronized.
| Value | Description |
|---|---|
| 0 | Writing a zero to this bit disables comparator n. |
| 1 | Writing a one to this bit enables comparator n. |