44.7.3 Comparator Control C
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLC |
| Offset: | 0x08 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PRESCALER[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PER[9:4] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PER[3:0] | WIDTH[9:8] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WIDTH[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 26:24 – PRESCALER[2:0] Prescaling Factor
These bits define the prescaling factor for the AC clock source (GCLK_AC) to generate the DAC sampling clock as shown in the following table.
| Value | Name | Description |
|---|---|---|
0x0 | DIV1 | Sampling rate is GCLK_AC (No division) |
0x1 | DIV2 | Sampling rate is GCLK_AC/2 |
0x2 | DIV4 | Sampling rate is GCLK_AC/4 |
0x3 | DIV8 | Sampling rate is GCLK_AC/8 |
0x4 | DIV16 | Sampling rate is GCLK_AC/16 |
0x5 | DIV32 | Sampling rate is GCLK_AC/32 |
0x6 | DIV64 | Sampling rate is GCLK_AC/64 |
0x7 | DIV128 | Sampling rate is GCLK_AC/128 |
Bits 21:12 – PER[9:0] DAC Sample and Hold Clock Period
These bits configure the sample and hold clock period. If PER is set to zero, no sample and hold DAC clock is generated.
Note: These bits are ignored if DACCTRLn.SHENn=0 (i.e. DAC continuous operation mode
is enabled).
Bits 9:0 – WIDTH[9:0] DAC Sample and Hold Clock Pulse Width
These bits configure the sample and hold clock pulse width. If WIDTH is set to zero, no sample and hold DAC clock is generated.
Note: These bits are ignored if DACCTRLn.SHENn=0 (i.e. DAC continuous operation mode
is enabled).