43.7.2 ADC Control Register B

Table 43-7. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	SWCNVEN				STRGEN	TRGSUSP	LSWTRG	GSWTRG
Access	R/W				R/W	R/W	R/W	R/W/HC
Reset	0				0	0	0	0


Bit	7	6	5	4	3	2	1	0
	SAMP	RQCNVRT			ADCHSEL[3:0]
Access	R/W	R/W/HC			R/W	R/W	R/W	R/W
Reset	0	0			0	0	0	0

Bit 15 – SWCNVEN Software - Controlled Conversion Enable bit

Note: When CTRLB.SWCNVEN=1, all channels sample and conversions are controlled exclusively by SAMP and RQCNVRT. All hardware triggers and GSWTRG and LSWTRG are disabled. It will place all of its channels under the exclusive control of the CTRLB.SAMP and CTRLB.RQCNVRT bits.

Value	Description
0	Software controlled conversions disable. Traditional ADC hardware triggers as defined by CHNCFG4n and CHNCFG5n will be active if enabled.
1	SAMP & RQCNVRT bits control entire ADC module sample and convert respectively for all channels on ADC module. Setting this bit blocks all other hardware triggers events defined by CHNCFG4n and CHNCFG5n.

Bit 11 – STRGEN Synchronous Trigger Enable bit

Note: This bit is ignored if CTRLB.SWCNVEN=1.

Value	Description
0	Disable automatic ADC hardware CTRLC.CNT counter driven synchronous ADC triggers.
1	Enable automated hardware synchronous trigger period defined by CTRLC.CNT register.

Bit 10 – TRGSUSP Trigger Suspend bit

Value	Description
0	Trigger suspend disabled. Triggers if enabled and selected will occur.
1	Blocks triggers from starting new ADC conversions but does not disable the ADC Modules or disable trigger capture, (i.e. persistent last trigger event is latched). If trigger capture during trigger suspend is not desired for any channels connected to a certain ADCn, then CTRLD.CHNENn must be cleared then set in that order prior to resetting TRGSUSP. Pulsing down and up CTRLD.CHNENn prior to resetting TRGSUSP will clear ALL pending triggers for ADCn.

Value

Description

0

Trigger suspend disabled. Triggers if enabled and selected will occur.

1

Blocks triggers from starting new ADC conversions but does not disable the ADC Modules or disable trigger capture, (i.e. persistent last trigger event is latched). If trigger capture during trigger suspend is not desired for any channels connected to a certain ADCn, then CTRLD.CHNENn must be cleared then set in that order prior to resetting TRGSUSP. Pulsing down and up CTRLD.CHNENn prior to resetting TRGSUSP will clear ALL pending triggers for ADCn.

Bit 9 – LSWTRG Level Global Software Trigger bit

Note:

This bit is ignored if SWCNVEN=1.
If SWCNVEN=0, this bit is NOT self-clearing and is meant to allow the user software to implement continuous sample/conversions on the associated analog input channel.

Value	Description
0	Global Level Software Trigger disabled.
1	Trigger A/D conversions for ADC analog input(s) "y" that have selected LSWTRG bit as the trigger signal via the associated CHNCFG4n.TRGSRC[y] or ADC CHNCFG50.TRGSRC[y] = 0b0010 or via the CORCTRLn.STRGSRC value where (n=ADC 0,1,2,3).

Bit 8 – GSWTRG Global Software Trigger bit

This software settable bit will trigger ADC sample/conversion sequences for ADC inputs that have selected the GSWTRG bit as the trigger signal via the associated CHNCFG4n.TRGSRC[y]= 0b0001 value, or via the CORCTRLn.STRGSRC value. This bit is auto cleared on the next APB clock cycle and is meant to implement single conversions on trigger edge-sensitive channels.

Note:

This bit is ignored if SWCNVEN=1.
If SWCNVEN=0, this bit is auto cleared by hardware after sampling cycle has been triggered and is meant to implement single sample/conversions on trigger edge-sensitive channels.

Value	Description
0	Disable Global Software Trigger.
1	If SWCNVEN=0, this bit is auto cleared by hardware after sampling cycle has been triggered and is meant to implement single sample/conversions on trigger edge-sensitive channels.

Bit 7 – SAMP Enable the Analog Mux Input and Start Sampling

Note:

This bit is ignored if SWCNVEN = 0.
ADCHSEL[3:0] must be initialized at or before when the SAMP bit is set.
The SAMP bit will keep the S&H circuit in Sample mode until the bit is cleared by the users software. Also, usage of the SAMP bit will cause settings of respective CORCTRLx.SAMC<9:0> bits to be ignored.
The SAMP bit is not a self-clearing bit and it is the responsibility of application software to clear this bit but only after setting the RQCNVRT bit to start the analog-to-digital conversion.
When the SAMP and RQCNVRT bits are used by software routines, all TRGSRCx<4:0> bits and STRGSRC<4:0> bits for the designated ADC module defined by ADCHSEL[3:0] should be set to ‘00000’ to disable all hardware triggers and prevent them from interfering with the software-controlled sampling command signal SAMP and with the software controlled trigger RQCNVRT.
The SAMP bit should only be used in conjunction with RQCNVRT for user software-controlled sampling and triggering.

Value	Description
0	ADC is not software-controlled sampling the ADC module and channel selected by ADCHSEL[3:0].
1	ADC is sampling and remain sampling for as long as user has this bit set in SW. The sampled analog input for a given ADCn module is defined by the channel selected by ADCHSEL[3:0] provided SWCNVEN = 1.

Bit 6 – RQCNVRT Request Individual ADC Conversion

Note:

If user’s software sets RQCNVRT = 1, an ADC conversion will begin immediately and terminate the sampling period defined by CORCTRLn.SAMC. This bit is cleared by hardware after the conversion is complete.
If SWCNVEN = 1, after setting this bit the users software must immediately clear the SAMP bit.
This bit is ignored if SWCNVEN = 0, (i.e. if software-controlled sample/conversions are disabled).

Value	Description
0	ADC is not converting if SWCNVEN = 1 or user previously set this bit and the previous ADC conversion is complete for the analog channel that was defined by ADCHSEL[3:0]
1	Terminate sampling and begin conversion of ADC and analog channel defined by ADCHSEL[3:0]. This bit is cleared by hardware when the conversion is complete.

Bits 3:0 – ADCHSEL[3:0] ADC Module Channel Input Select bits

This binary encoded bit field selects the ADC analog input to be sampled and converted respectively by the SAMP and RQCNVRT bit if SWCNVEN = 1.

Note: These bits are ignored if SWCNVEN = 0.


ADC Modules	ADCHSEL[3:0]	Analog Channel Input
ADC (AIN14:0)	0x0	VINP0
	0x1	VINP1
	0x2	VINP2
	0x3	VINP3
	0x4	VINP4
	0x5	VINP5
	0X6	VINP6
	0x7	VINP7
	0x8	VINP8
	0x9	VINP9
	0xA	VINP10
	0xB	VINP11
	0xC	Temp Sensor
	0xD	1.2v IVREF

Name:	CTRLB
Offset:	0x4
Reset:	0x00000000
Property:	Write-Synchronized via SYNCBUSY.CTRLB