43.7.15 ADC COR Channel Ready DATA ID Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CORCHDATAID |
| Offset: | 0xD0 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protected, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHRDYID[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 3:0 – CHRDYID[3:0] ADC Channel Read ID
Input Channel Index k:
For ADC, set value to input channel index, k,0 ≤ k ≤ (Sn-1) for status register CHNRDYDAT to display the current values of configuration bits and the last converted output data or written by the user to display the channel.
Note:
- ADC supports external analog inputs VINP[11:0] and internal inputs VINP[14:12]. VINP[11:10] are not available in the 64-pin package.
- Selecting unimplemented input channels on a given ADCn will return a bus error with the data (32’h00000000).
| Value | Description |
|---|---|
| 1110 | analog input channel 14(1) |
| ... | ... |
| 0010 | analog input channel 2 |
| 0001 | analog channel 1 |
| 0000 | analog channel 0 |