43.7.19 ADC Core Synchronization Register

Note: The following GCLK-clocked registers are “Enable Write Protected”:
  • CTRLC
  • CTRLD
  • CORCTRL0
  • CHNCFG10
  • CHNCFG20
  • CHNCFG30
  • CHNCFG40
  • CHNCFG50
  • CALTRL0
  • FLTCTRL0

Therefore, they do not require a SyncBusy bit. These registers are write-disabled when the CTRLA.ENABLE bit is set to enable the ADC. They can only be changed when the ADC is disabled (CTRLA.ENABLE = 0). The user must completely configure the ADC and then enable the ADC by setting CTRLA.ENABLE = 1.

Table 43-24. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: SYNCBUSY
Offset: 0xE8
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
      CTRLBENABLESWRST 
Access RRR 
Reset 000 

Bit 2 – CTRLB Synchronization Busy bit

For the GCLK-based register CTRLB:

When Hardware sets this bit, no writes are permitted to the CTRLB register.

Bit 1 – ENABLE ENABLE Synchronization Busy bit

For GCLK-based register bit CTRLA.ENABLE:

When Hardware sets this bit, no writes are permitted to the CTRLA.ENABLE register.

Bit 0 – SWRST Software Reset Busy bit

Note:
  1. Typically, when the SWRST is written, the bit is auto-cleared the next APB clock cycle after. However, the SYNCBUSY.SWRST bit is set and stays set until the reset in the GCLK domain is completed. Therefore, the user must poll the SYNCBUSY register to know when the operation is complete.
  2. Care must be taken during the APB reset phase, because potentially the external clock (GCLK) may not present.
  3. During a SWRST, access to registers or bits without SWRST are disallowed until SYNCBUSY.SWRST is cleared by hardware.