43.7.8 ADC Channel Configuration Registers 3
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CONFIG[0].CHNCFG3 |
| Offset: | 0x2C |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protected, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SIGN14 | SIGN13 | SIGN12 | SIGN11 | SIGN10 | SIGN9 | SIGN8 | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SIGN7 | SIGN6 | SIGN5 | SIGN4 | SIGN3 | SIGN2 | SIGN1 | SIGN0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIFF4 | DIFF2 | DIFF0 | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 – SIGNk Signed Data Output Format Enable for channel k
Bit 30: SIGN14 Signed Data Output Format Enable for ADC Module 0, analog input AIN14
Bit 29: SIGN13 Signed Data Output Format Enable for ADC Module 0, analog input AIN13
Bit 28: SIGN12 Signed Data Output Format Enable for ADC Module 0, analog input AIN12
Bit 27: SIGN11 Signed Data Output Format Enable for ADC Module 0, analog input AIN11 (1)
Bit 26: SIGN10 Signed Data Output Format Enable for ADC Module 0, analog input AIN10 (1)
Bit 25: SIGN9 Signed Data Output Format Enable for ADC Module 0, analog input AIN9
Bit 24: SIGN8 Signed Data Output Format Enable for ADC Module 0, analog input AIN8
Bit 23: SIGN7 Signed Data Output Format Enable for ADC Module 0, analog input AIN7
Bit 22: SIGN6 Signed Data Output Format Enable for ADC Module 0, analog input AIN6
Bit 21: SIGN5 Signed Data Output Format Enable for ADC Module 0, analog input AIN5
Bit 20: SIGN4 Signed Data Output Format Enable for ADC Module 0, analog input AIN4
Bit 19: SIGN3 Signed Data Output Format Enable for ADC Module 0, analog input AIN3
Bit 18: SIGN2 Signed Data Output Format Enable for ADC Module 0, analog input AIN2
Bit 17: SIGN1 Signed Data Output Format Enable for ADC Module 0, analog input AIN1
Bit 16: SIGN0 Signed Data Output Format Enable for ADC Module 0, analog input AIN0
- These bits are not available in the 64-pin package.
| Value | Description |
|---|---|
| 0 | Output format is unsigned |
| 1 | Output format is signed |
Bit 4 – DIFF4 Differential Mode Enable for channel k
Bit 4: DIFF4 Differential Mode Enable for ADC Module 0, analog input AIN4
| Value | Description |
|---|---|
| 0 | Channel is connected in single-ended mode |
| 1 | Channel is connected in differential mode |
Bit 2 – DIFF2 Differential Mode Enable for channel k
Bit 2: DIFF2 Differential Mode Enable for ADC Module 0, analog input AIN2
| Value | Description |
|---|---|
| 0 | Channel is connected in single-ended mode |
| 1 | Channel is connected in differential mode |
Bit 0 – DIFF0 Differential Mode Enable for channel k
Bit 0: DIFF0 Differential Mode Enable for ADC Module 0, analog input AIN0
| Value | Description |
|---|---|
| 0 | Channel is connected in single-ended mode |
| 1 | Channel is connected in differential mode |