50.5.13.10 Framed SPI Support, Subset of TDM

This mode is enabled by setting SPIxCTRL_*.TDM_EN = 1, SPIxCTRL_*.MSTEN = 1 and SPIxCTRL_*.FRMMST = 0. The serial clock is output at the SCK pin, regardless of whether the module is transmitting, and the SS pin is driven high on the next transmit edge of the SCK clock when the SPIx- BUF is written. Data will start transmitting on the subsequent transmit edge of the SPI clock.

This mode is enabled by setting SPIxCTRL_*.TDM_EN = 1, SPIxCTRL_*.MSTEN = 1and SPIxCTRL_*.FRMMST = 1. The SCK pin is an output while the SS pin is an input. When the SS pin is sampled high or low (SPIxCTRL_*.FRMPOL = 1/0), the data is transmitted on the subsequent transmit edge of the SPI clock. The user must make sure that the correct to-be-transmitted data is loaded into SPIx- BUF before the frame sync pulse is received at the SS pin.

This mode is enabled by setting SPIxCTRL_*.TDM_EN = 1, SPIxCTRL_*.MSTEN = 0 and SPIxCTRL_*.FRMMST = 0. The input clock at the SCK pin is continuous while the SS pin is an output.

This mode is enabled by setting SPIxCTRL_*.TDM_EN = 1, SPIxCTRL_*.MSTEN = 0 and SPIxCTRL_*.FRMMST = 1. Both SCK and SS pins are inputs.

SCK becomes an output when SPIxCTRL_*.TDM_EN = 1 and SPIxCTRL_*.MSTEN = 1. SCK becomes an input when SPIxCTRL_*.TDM_EN = 1 and SPIxCTRL_*.MSTEN = 0. In both cases, the source clock provided to the SCK pin is assumed to be free-running.

The polarity of the clock is selected by the SPIxCTRL_*.CPOL and SPIxCTRL_*.CPHA bits. Since the clock does not stop, the specification of transmission on transition from active to idle or idle to active clock states is moot. The end result is that there are only 2 actual cases of clock although the CPOL and CPHA bits can specify 4 cases.

When (CPOL = 0, CPHA = 1) or (CPOL = 1, CPHA = 0) the frame sync pulse output and the SDO data out- put change on the rising edge of the SCK clock.

When (CPOL = 1, CPHA = 1) or (CPOL = 0, CPHA = 0), the frame sync pulse output and the SDO data out- put change on the falling edge of the SCK clock.

Framed SPI mode works in all 8/16/32-bit environments. The frame sync pulse is generated for every 8/16/32-bits of data transmitted/received in 8/16/32-bit modes, respectively.

A frame error occurs when the SPI detects a second frame sync pulse during a burst transfer. If this SPI is a frame host, it does not generate more than one frame sync pulse per frame burst. However, if the SPI is the frame client, it could receive multiple frame sync pulses if the data transmit size (as defined by FRMCNT) differs between it and the frame host. In such a case, the SPI captures the occurrence in the FRMERR bit, but continues with the original transfer count. If FRMERREN = 1, then that occurrence generates an error interrupt.

When the macro is in frame host mode (SPIxCTRL_*.FRMMST = 0), the frame sync pulse is initiated when the user software writes to SPIxBUF, thereby loading the SPIxTXB register with the transmit data. Depending on SPIxCTRL_*.FRMCOINC, the data is transferred to SPIxSR and the send sequence begins. At the end of the send sequence, the data received is transferred to SPIxRXB and is available for the software to read from SPIxBUF.

When the macro is in frame client mode (SPIxCTRL_*.FRMMST = 1), the frame sync pulse is generated by an external source. When the macro samples the frame sync pulse, it transfers the contents of the SPIxTXB register to SPIxSR and the data transmission/reception begins. After the host/client transfer finishes, the received data is moved to SPIxRXB, which then can be read by the user software from SPIxBUF.

Event generation and timing in Framed SPI mode are similar to that of the normal SPI mode.

For enhance framed SPI mode, the SPIxCTRL_*.FRMCNT register bits determines how many characters are sent/received for every frame sync pulse. The entire transaction is called a frame. If SPIxCTRL_*.FRMCNT = “000”, then a fsync pulse is generated for every data/character transmission. A simple case of generating a frame sync pulse for every 2 data characters (SPIxCTRL_*.FRMCNT= “1”).

In addition, the width of the frame sync pulse can be programmed to be either one clock wide or one character wide by programming SPIxCTRL_*.FRMSYPW.

This mode is the same as the other non-framed host modes, but with the additional ability to drive a client select directly by using the FSYNC pin. In this mode, the SPIxCTRL_*.MSSEN and SPIxC- TRL_*.FRMPOL control bits determine the activation of the client select signal. The client select signal will be driven approximately one SCK cycle before and after the data transmission occurs.

If the transmit buffer is empty when the SPI must load the send register to start (in the case of Framed Client) or continue (for either Framed Host or Client) a transfer, the SPI immediately sets SPITUR to indicate an underrun condition. If SPITUREN=1, the SPI asserts its error interrupt (to the interrupt controller).

While the SPI is in an underrun condition, the SPI transmits all zeroes until the end of the transaction as defined by FRMCNT. If the SPI is a frame client, another frame sync pulse can occur before the condition clears. In this case the SPI continues to transmit zeros. If the SPI is a frame host, it then waits for software to clear the under-run condition before initiating another sync pulse regardless of the state of the SPIxTXB.

For cases when software does not care or need to know about the underrun condition, IGNTUR = 1 provides the serial engine the ability to ignore the under- run. When an underrun occurs, the SPI still sets the SPIxSTAT.SPITUR flag and obeys SPITUREN. Once SPITUR is set, it remains so until software clears it or SPIxCTRL_*.ENABLE = 0.

When the SPI is either a frame client or a frame host, an underrun event still causes the SPI to transmit zeros until the end of the frame as defined by FRMCNT. However, with IGNTUR = 1, the SPI can re-sample the underrun condition and continue to transmit data at each frame boundary.

If the SPI is a frame host, new data written to the SPIxTXB during a frame when an underrun condition exists does not get transmitted during that frame. But, the SPI evaluates the SPIxTXB continuously after the last frame. If data is in it, the SPI generates a frame sync and transmits the data.

If the SPI is a frame client, its transmit logic evaluates SPIxTXB for underrun during the next sync pulse. If the SPIxTXB contains data at the onset of the sync pulse,the SPI transmits that data. If not, the SPI transmits zero data until the end of the frame.

When IGNTUR=1 and SPITUR=1, a software write of zero (0) to the SPITUR bit clears the condition; but it does NOT flush data in the SPIxTXB, which may have been put in after the condition occurred.

When IGNTUR=0 and SPITUR=1, a software write of zero (0) to the SPITUR bit clears the condition; and it flushes the data in the SPIxTXB. The SPI ignores writes to the SPIxTXB after clearing SPITUR until a read of SPIxSTAT when SPITUR = 0. This behavior ensures that a data service routine that is interrupted long enough to cause SPITUR, can’t inadvertently start a new framed transaction after the SPI error handler has cleared the error.