50.5.13.1 I8S (I2S) Standard Mode AM824 24-bit Raw Audio Format Mode (16, 20 24 Sample Data) AUDMOD=00, AUDFMT[2:0]=101(001), AUDWD_MODE[1:0]=10

In I8S (I2S) AM824 mode, A frame transmits left channels first then right channels. For the left channels, the data is transmitted while LRC is low and for the right channels, the data is transmitted while LRC is high. The transmitter drives the audio data’s MSB on the first falling edge of SCK after an LRC transition. The receiver samples the MSB on the second rising edge of SCK.

For I8S standard mode AM824 24-bit raw audio for- mat, the configuration bits in SPIxCTRL_* must be set as follows: AUDMOD=00, AUDEN=1, FRMPOL=0, CPOL=1, CPHA=1, FRMSYPW=0100, FRMCNT=011, AUDFMT[2:0]=101, AUDWD_-

MODE[1:0]=10, FRMCOINC=0. These values set SDO and LRC transitions to occur on the falling edge of SCK and sampling of SDI to occur on the rising edge of SCK. It also starts a frame with LRC falling edge transition. The following figure shows the waveform for this 24 bit configuration with relationship of the LRC with Falling Edge of LRC with transmit on the next falling edge of CLK and sampling on the rising edge of CLK FRMPOL=0, CPOL=1, CPHA=1, FRMCOINC=0.

Figure 50-22. I8S Standard Timing with Falling Edge Transition of LRC

The following figure shows an expanded view of this waveform with, starting of a frame on the falling edge transition of LRC. AM824 formats with 20, 16 bit raw audio are similar and are specified using the AUDWD_MODE[1:0] register set to 01 and 00.

Figure 50-23. Expanded I8S Standard Timing with Falling Edge Transition of LRC

The following figure shows relationship of the LRC with rising edge of CLK with transmit on falling edge of CLK and sampling on the rising edge of CLK FRMPOL=1, CPOL=0, CPE=1,FRMCOINC=1.

Figure 50-24. I8S Standard Timing with Rising Edge Transition of LRC and Sample Data on Falling Edge of CLK AM824 - Raw Audio Format

An I2S example for AM824 would be the same as the I8S in the previous figure. With the differences of 2 channels in-place of 8 channels and the frame would be 64 bit clocks in stead of 256 bit clocks. For I2S standard mode AM824 24-bit raw audio format, the configuration bits in SPIxCTRL_* must be set as fol- lows: AUDMOD=00, AUDEN=1, FRMPOL=0, CPOL=1, CPHA=1, FRMSYPW=0001, FRMCNT=001, AUDFMT[2:0]=001, AUDWD_MODE[1:0]=10, FRMCOINC=0.

As the data is serially sent in/out of the peripheral only the 24(20/16) bit sample is sent and the remaining lower bits not defined by the 16, 20 or 24 bit sample (total of 32 bits in a quadlet/word) are don’t care values sent out. The don’t care bits are sent out to make a complete 32-bit word per channel to keep channel alignment with the LRC. As the serial data is sent into the peripheral, the 32-bit word is reformed with the proper label for the AM824 format and 24(20/16) bit sample to form a AM824 24, 20, 16 bit sample raw for- mat to store in memory as shown in the following figure.

Figure 50-25. AM824 Packet Format