34.7.5.2 Control B
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLB |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Enable-Protected, Write-Synchronized |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FIFOCLR[1:0] | RXEN | ||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| AMODE[1:0] | MSSEN | SSDE | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PLOADEN | CHSIZE[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 23:22 – FIFOCLR[1:0] FIFO Clear
When these bits are set, the corresponding FIFO will be cleared. The bits will automatically clear when SYNCBUSY.CTRLB = 0.
These bits are not enable-protected.
| FIFOCLR[1:0] | Name | Description |
|---|---|---|
| 0x0 | NONE | No action |
| 0x1 | TXFIFO | Clear TX FIFO |
| 0x2 | RXFIFO | Clear RX FIFO |
| 0x3 | BOTH | Clear both TX/RX FIFO |
Bit 17 – RXEN Receiver Enable
Writing '0' to this bit will disable the SPI receiver immediately. The receive buffer will be flushed, data from ongoing receptions will be lost and STATUS.BUFOVF will be cleared.
Writing '1' to this bit when the SPI is disabled will set it immediately. When the SPI is enabled, RXEN will be cleared, SYNCBUSY.CTRLB will be set and remain set until the receiver is enabled. When the receiver is enabled RXEN will read back as '1'.
Writing '1' to RXEN when the SPI is enabled will set SYNCBUSY.CTRLB, which will remain set until the receiver is enabled, and RXEN will read back as '1'.
This bit is not enable-protected.
| Value | Description |
|---|---|
| 0 | The receiver is disabled or being enabled. |
| 1 | The receiver is enabled or it will be enabled when SPI is enabled. |
Bits 15:14 – AMODE[1:0] Address Mode
These bits set the Client Addressing mode when the frame format (CTRLA.FORM) with address is used. They are unused in Host mode.
| AMODE[1:0] | Name | Description |
|---|---|---|
| 0x0 | MASK | ADDRMASK is used as a mask to the ADDR register |
| 0x1 | 2_ADDRS | The client responds to the two unique addresses in ADDR and ADDRMASK |
| 0x2 | RANGE | The client responds to the range of addresses : ADDRMASK < address < ADDR |
| 0x3 | - | Reserved |
Bit 13 – MSSEN Host Client Select Enable
This bit enables hardware Client Select (SS) control.
| Value | Description |
|---|---|
| 0 | Hardware SS control is disabled. |
| 1 | Hardware SS control is enabled. |
Bit 9 – SSDE Client Select Low Detect Enable
This bit enables wake-up when the Client Select (SS) pin transitions from high to low.
| Value | Description |
|---|---|
| 0 | SS low detector is disabled. |
| 1 | SS low detector is enabled. |
Bit 6 – PLOADEN Client Data Preload Enable
Setting this bit will enable preloading of the Client Shift register when there is no transfer in progress. If the SS line is high when DATA is written, it will be transferred immediately to the Shift register.
Bits 2:0 – CHSIZE[2:0] Character Size
| CHSIZE[2:0] | Name | Description |
|---|---|---|
| 0x0 | 8BIT | 8 bits |
| 0x1 | 9BIT | 9 bits |
| 0x2-0x7 | - | Reserved |