34.7.5.8 Status

Table 34-33. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: STATUS
Offset: 0x1A
Reset: 0x0000
Property: –

Bit 15141312111098 
     LENERR    
Access R/W 
Reset 0 
Bit 76543210 
     TURBUFOVF   
Access R/WR/W 
Reset 00 

Bit 11 – LENERR Transaction Length Error

This bit is set in client mode when the length counter is enabled (LENGTH.LENEN=1) and the transfer length while SS is low is not a multiple of LENGTH.LEN.

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear it.

ValueDescription
0No Length Error has occurred.
1A Length Error has occurred.

Bit 3 – TUR Frame Transmit Underrun

This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set when an underflow condition is detected in frame mode. Writing '0' to this bit has no effect. Writing '1' to this bit sends a request to clear it. It will be actually cleared after the DATA buffer is flushed.

ValueDescription
0No Underrun has occurred.
1A Underrun has occurred.

Bit 2 – BUFOVF Buffer Overflow

Reading this bit before reading DATA will indicate the error status of the next character to be read.

This bit is cleared by writing '1' to the bit or by disabling the receiver.

This bit is set when a Buffer Overflow condition is detected. See also CTRLA.IBON for overflow handling.

When set, the corresponding RxDATA will be zero.

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear it.

ValueDescription
0No Buffer Overflow has occurred.
1A Buffer Overflow has occurred.