43.7.3 LUT Control n
Note: LUTCTRLn register is Enable
Protected when CCL.LUTCTRLn.ENABLE = 1.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | LUTCTRLn |
| Offset: | 0x08 + n*0x04 [n=0..3] |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Enable-protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TRUTH[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| LUTEO | LUTEI | INVEI | INSEL2[3:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| INSEL1[3:0] | INSEL0[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EDGESEL | FILTSEL[1:0] | ENABLE | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 31:24 – TRUTH[7:0] Truth Table
These bits define the value of truth logic as a function of inputs IN[2:0].
Bit 22 – LUTEO LUT Event Output Enable
| Value | Description |
|---|---|
| 0 | LUT event output is disabled. |
| 1 | LUT event output is enabled. |
Bit 21 – LUTEI LUT Event Input Enable
| Value | Description |
|---|---|
| 0 | LUT incoming event is disabled. |
| 1 | LUT incoming event is enabled. |
Bit 20 – INVEI Inverted Event Input Enable
| Value | Description |
|---|---|
| 0 | Incoming event is not inverted. |
| 1 | Incoming event is inverted. |
Bits 8:11, 12:15, 16:19 – INSELy y = [0,1,2]. LUT Input y Source Selection
These bits select the LUT input y source:
Note: TCC6 and TCC7 connections are unavailable for devices
that do not have those TCC instances.
| Value | Name | Description |
|---|---|---|
| 0x0 | MASK | Masked input |
| 0x1 | FEEDBACK | Feedback input source |
| 0x2 | LINK | Linked LUT input source |
| 0x3 | EVENT | Event input source |
| 0x4 | IO | I/O pin input source |
| 0x0B - 0x0F | Reserved | Reserved |
| 0x5 | 0x6 | 0x7 | 0x8 | 0x9 | 0xA | |
|---|---|---|---|---|---|---|
| LUT0.IN0 | AC0 output | SERCOM0 padout[0] | TCC0 WO0 | TCC0 WO4 | TCC4 WO0 | TCC5 WO0 |
| LUT0.IN1 | AC0 output | SERCOM0 padout[0] | TCC0 WO1 | TCC0 WO5 | TCC4 WO1 | TCC5 WO1 |
| LUT0.IN2 | AC0 output | SERCOM0 padout[0] | TCC0 WO2 | TCC0 WO6 | TCC4 WO0 | TCC5 WO0 |
| LUT1.IN0 | AC1 output | SERCOM1 padout[0] | TCC1 WO0 | TCC1 WO4 | TCC6 WO0 | TCC7 WO0 |
| LUT1.IN1 | AC1 output | SERCOM1 padout[0] | TCC1 WO1 | TCC1 WO5 | TCC6 WO1 | TCC7 WO1 |
| LUT1.IN2 | AC1 output | SERCOM1 padout[0] | TCC1 WO2 | TCC1 WO6 | TCC6 WO0 | TCC7 WO0 |
| LUT2.IN0 | AC0 output | SERCOM2 padout[0] | TCC2 WO0 | TCC2 WO4 | TCC0 WO0 | TCC1 WO0 |
| LUT2.IN1 | AC0 output | SERCOM2 padout[0] | TCC2 WO1 | TCC2 WO5 | TCC0 WO1 | TCC1 WO1 |
| LUT2.IN2 | AC0 output | SERCOM2 padout[0] | TCC2 WO2 | TCC2 WO6 | TCC0 WO0 | TCC1 WO0 |
| LUT3.IN0 | AC1 output | SERCOM3 padout[0] | TCC3 WO0 | TCC3 WO4 | TCC2 WO0 | TCC3 WO0 |
| LUT3.IN1 | AC1 output | SERCOM3 padout[0] | TCC3 WO1 | TCC3 WO5 | TCC2 WO1 | TCC3 WO1 |
| LUT3.IN2 | AC1 output | SERCOM3 padout[0] | TCC3 WO2 | TCC3 WO6 | TCC2 WO0 | TCC3 WO0 |
Bit 7 – EDGESEL Edge Selection
| Value | Description |
|---|---|
| 0 | Edge detector is disabled. |
| 1 | Edge detector is enabled. |
Bits 5:4 – FILTSEL[1:0] Filter Selection
These bits select the LUT output filter options:
Filter Selection
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Filter disabled |
| 0x1 | SYNCH | Synchronizer enabled |
| 0x2 | FILTER | Filter enabled |
| 0x3 | - | Reserved |
Bit 1 – ENABLE LUT Enable
| Value | Description |
|---|---|
| 0 | The LUT is disabled. |
| 1 | The LUT is enabled. |