6 Signal Description

The following tables provide details on signal names classified by peripherals.

Note: IOSET Configurations – The PIC32CK device family has multiple peripheral instances, mapped to different I/O locations. Each peripheral I/O location is called IOSET and for a given peripheral, signals from different IOSET cannot be mixed.

For a given peripheral with two pads, PAD0 and PAD1:

Valid: PAD0 and PAD1 in the same IOSETn
Invalid: PAD0 in IOSETx and PAD1 in IOSETy

Note:

Bolded pins are only available on PIC32CK1012 variant devices.
64 TQFP package is identical to 64 VQFN package for signal description.

Table 6-1. Analog Comparator (AC) Signals
PIN NAME	PIN NUMBER					PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	PIN TYPE	FUNCTION TYPE	DESCRIPTION
AC_AIN0	8/10	10/13	15/22	25	M9	I	Analog	Comparator 0 and 1 external analog inputs
AC_AIN1	9/11	11/14	16/23	26	M10	I	Analog
AC_AIN2	33	41	60	85	D8	I	Analog
AC_AIN3	34	42	61	86	D7	I	Analog
AC_CMP0	12	15/44	24/63	35/80/94	B8/C6/K12	O	Analog	Comparator 0 Output
AC_CMP1	13	16	25/64	36/81/95	A8/C7/K11	O	Analog	Comparator 1 Output

Table 6-2. Analog-to-Digital Controller (ADC) Signals
PIN NAME	PIN NUMBER					PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	PIN TYPE	FUNCTION TYPE	DESCRIPTION
ADC_VINM0	-	9	14	24	M8	I	Analog	ADC module analog inputs
ADC_VINM2	9	11	16	26	M10	I	Analog
ADC_VINM4	-	-	18	28	M11	I	Analog
ADC_VINP0	-	8	13	23	K7	I	Analog
ADC_VINP1	-	9	14	24	M8	I	Analog
ADC_VINP2	8	10	15	25	M9	I	Analog
ADC_VINP3	9	11	16	26	M10	I	Analog
ADC_VINP4	-	12	17	27	K8	I	Analog
ADC_VINP5	10	13	22	33	L12	I	Analog
ADC_VINP6	11	14	23	34	L11	I	Analog
ADC_VINP7	12	15	24	35	K12	I	Analog
ADC_VINP8	13	16	25	36	K11	I	Analog
ADC_VINP9	14	17	26	37	K10	I	Analog
ADC_VINP10	-	-	28	39	J9	I	Analog
ADC_VINP11	-	-	29	40	J10	I	Analog
ADC_VREFP0	15	18	27	38	K9	I	Analog

Table 6-3. Controller Area Network (CAN) Signals
PIN NAME	PIN NUMBER					IOSET	PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	IOSET	PIN TYPE	FUNCTION TYPE	DESCRIPTION
CAN0_RX	-	31	49	71	E12	1	I	ST	CAN0_FD Receive
CAN0_RX	29/34	36/42	54/61	76	B12	2
CAN0_RX	-	-	46	68	F11	3
CAN0_RX	15	18	27	60	C9	4
CAN0_RX	-	-	-	132	G2	5
CAN0_TX	-	30	48	70	E11	1	O	CMOS	CAN0_FD Transmit
CAN0_TX	28/33	35/41	53/60	75	C12	2
CAN0_TX	-	-	45	65	C10	3
CAN0_TX	14	17	26	59	E10	4
CAN0_TX	-	-	-	131	G3	5
CAN1_RX	-	-	-	38	K9	1	I	ST	CAN1_FD Receive
CAN1_RX	-	42	61	86	D7	2
CAN1_RX	-	-	-	62	C8	3
CAN1_RX	-	-	-	134	J1	4
CAN1_TX	-	17	26	37	K10	1	O	CMOS	CAN1_FD Transmit
CAN1_TX	-	41	60	85	D8	2
CAN1_TX	-	-	-	61	D10	3
CAN1_TX	-	-	-	133	H2	4

Table 6-4. Configurable Custom Logic (CCL) Signals
PIN NAME	PIN NUMBER					IOSET	PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	IOSET	PIN TYPE	FUNCTION TYPE	DESCRIPTION
LUT0_IN0	17	20/29	31/47	69	F12	1	I	Digital Input	Lookup Table 0, Input 0
LUT0_IN0	-	-	-	60	C9	2	I	Digital Input	Lookup Table 0, Input 0
LUT0_IN1	18	21/30	32/48	70	E11	1	I	Digital Input	Lookup Table 0, Input 1
LUT0_IN1	-	-	-	61	D10	2	I	Digital Input	Lookup Table 0, Input 1
LUT0_IN2	42	31/53	49/88	71	E12	1	I	Digital Input	Lookup Table 0, Input 2
LUT0_IN2	-	-	-	62	C8	2	I	Digital Input	Lookup Table 0, Input 2
LUT1_IN0	36	45	68	101	B5	1	I	Digital Input	Lookup Table 1, Input 0
LUT1_IN0	-	-	-	87	A11	2	I	Digital Input	Lookup Table 1, Input 0
LUT1_IN1	37	46	71	104	A4	1	I	Digital Input	Lookup Table 1, Input 1
LUT1_IN1	-	-	-	88	B10	2	I	Digital Input	Lookup Table 1, Input 1
LUT1_IN2	33	41/47	60/72	105	A3	1	I	Digital Input	Lookup Table 1, Input 2
LUT1_IN2	-	-	-	92	A10	2	I	Digital Input	Lookup Table 1, Input 2
LUT2_IN0	14	17/61	26/97	141	H3	1	I	Digital Input	Lookup Table 2, Input 0
LUT2_IN0	-	-	-	130	F2	2	I	Digital Input	Lookup Table 2, Input 0
LUT2_IN1	15	18/62	27/98	142	J4	1	I	Digital Input	Lookup Table 2, Input 1
LUT2_IN1	-	-	-	131	G3	2	I	Digital Input	Lookup Table 2, Input 1
LUT2_IN2	20	23/63	36/99	143	J5	1	I	Digital Input	Lookup Table 2, Input 2
LUT2_IN2	-	-	-	132	G2	2	I	Digital Input	Lookup Table 2, Input 2
LUT3_IN0	-	8	13	23	K7	1	I	Digital Input	Lookup Table 3, Input 0
LUT3_IN0	-	-	8	12	L5	2	I	Digital Input	Lookup Table 3, Input 0
LUT3_IN1	-	9	14	24	M8	1	I	Digital Input	Lookup Table 3, Input 1
LUT3_IN1	-	-	9	13	M5	2	I	Digital Input	Lookup Table 3, Input 1
LUT3_IN2	8	10	15	25	M9	1	I	Digital Input	Lookup Table 3, Input 2
LUT3_IN2			10	14	K6	2	I	Digital Input	Lookup Table 3, Input 2
LUT0_OUT	1/22	1/25/32	1/39/50	72	D12	1	O	Digital Output	Lookup Table 0 Output
LUT0_OUT	-	-	-	63	G11	2	O	Digital Output	Lookup Table 0 Output
LUT1_OUT	-	48	73	106	A2	1	O	Digital Output	Lookup Table 1 Output
LUT1_OUT	-	-	-	93	A9	2	O	Digital Output	Lookup Table 1 Output
LUT2_OUT	34	42/64	61/100	144	J3	1	O	Digital Output	Lookup Table 2 Output
LUT2_OUT	-	-	-	133	H2	2	O	Digital Output	Lookup Table 2 Output
LUT3_OUT	9/21	11/24	16/37	26	M10	1	O	Digital Output	Lookup Table 3 Output
LUT3_OUT	-	-	11	15	J6	2	O	Digital Output	Lookup Table 3 Output

Table 6-5. DEBUG – SW-2 wire, JTAG, Trace, and Programming/Debugging Signals
PIN NAME	PIN NUMBER					PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	PIN TYPE	FUNCTION TYPE	DESCRIPTION
TDI	1	1	1	1	L2	I	ST	Debug/Scan JTAG Data Input
TDO	2	2	2	2	L3	O	CMOS	Debug/Scan JTAG Data Out
TMS	3	3	3	3	K3	I	ST	Debug/Scan JTAG Mode Select
TCK	4	4	4	4	K4	I	ST	Debug/Scan JTAG Clock
SWO	2	2	2	2	L3	O	CMOS	Debug Serial Wire Output Data
SWDIO	3	3	3	3	K3	I/O	ST/CMOS	Debug Serial Wire Data In/Out
SWCLK	4	4	4	4	K4	I	ST	Debug Serial Wire Input Clock
TRACECLK	-	-	11	15	J6	I	ST	Debug Trace Clock
TRACE_DATA0	-	-	12	16	M6	I/O	ST/CMOS	Debug Instruction Trace Data 0
TRACE_DATA1	-	-	10	14	K6			Debug Instruction Trace Data 1
TRACE_DATA2	-	-	9	13	M5			Debug Instruction Trace Data 2
TRACE_DATA3	-	-	8	12	L5			Debug Instruction Trace Data 3
RESET	5	5	5	5	L4	I	ST	MCU Reset input (Active Low)

Table 6-6. External Bus Interface (EBI) Signals
PIN NAME	PIN NUMBER			PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	100 TQFP	144 TQFP	144 TFBGA	PIN TYPE	FUNCTION TYPE	DESCRIPTION
EBI_A2	74	107	B3	O	CMOS	EBI Address A[23:1} (External BUS interface)
EBI_A3	67	100	A5
EBI_A4	66	99	A6
EBI_A5	65	98	B6
EBI_A6	64	95	A8
EBI_A7	59	84	B9
EBI_A8	58	82	C4
EBI_A9	55	77	B11
EBI_A10	54	76	B12
EBI_A11	53	75	C12
EBI_A12	52	74	C11
EBI_A13	51	73	D11
EBI_A14	50	72	D12
EBI_A15	49	71	E12
EBI_A16	97	93/141	A9/H3
EBI_A17	94	92/138	A10/L1
EBI_A18	93	63/137	G11/K2
EBI_A19	88	62/121	C8/D3
EBI_A20	-	61	D10
EBI_A21	-	60	C9
EBI_A22	-	59	E10
EBI_A23	-	96	A7
EBI_D0	8	12	L5	I/O	CMOS	EBI Data Bus [D15:0] (External BUS interface)
EBI_D1	9	13	M5
EBI_D2	10	14	K6
EBI_D3	11	15	J6
EBI_D4	12	16	M6
EBI_D5	13	23	K7
EBI_D6	14	24	M8
EBI_D7	15	25	M9
EBI_D8	16	26	M10
EBI_D9	17	27	K8
EBI_D10	28	39	J9
EBI_D11	29	40	J10
EBI_D12	37	51	G8
EBI_D13	38	52	G10
EBI_D14	39	53	H9
EBI_D15	40	54	G9
EBI_NBS0_A0	48	70	E11	O	CMOS	EBI Address A0 or Byte Select 0
EBI_NBS1_NWR1	47	69	F12	O	CMOS	EBI Byte Select1 or Byte Write1 (Active Low)
EBI_NBS2_NWR2_A1	75	108	B4	O	CMOS	EBI Byte Select2 or Byte Write2 (Active Low) or Address A1
EBI_NCS0	91	88/135	B10/J2	O	CMOS	EBI Chip Select 0 (Active Low)
EBI_NCS1	98	83/142	C5/J4			EBI Chip Select 1 (Active Low)
EBI_NCS2	-	97	B7			EBI Chip Select 2 (Active Low)
EBI_NCS3	-	126	F3			EBI Chip Select 3 (Active Low)
EBI_NRD	41	55	F10	O	CMOS	EBI Read (Active Low)
EBI_NWAIT	23/100	34/81/144	L11/C7/J3	O	CMOS	EBI WAIT output (Active Low)
EBI_NWE_NWR0	92	87/136	A11/K1	O	CMOS	EBI Write Enb or Write0 (Active Low)

Table 6-7. External Interrupt Controller (EIC) Signals
PIN NAME	PIN NUMBER					PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	PIN TYPE	FUNCTION TYPE	DESCRIPTION
EIC_EXTINT0	14/26/40	17/33/51	11/26/45/ 51/65/86	15/37/65/73/ 98/119/127	B6/C10/D11/E1/ E2/J6/K10	I	ST	External Interrupt 0 input
EIC_EXTINT1	2/15/27/41	2/18/34/52	2/12/27/ 46/52/66/87	2/16/68/74/ 99/120/130	A6/C11/F1/F2/ F11/L3/M6	I	ST	External Interrupt 1 input
EIC_EXTINT2	3/17/28	3/20/35	3/18/31/ 53/67	3/28/41/45/ 75/100/131	A5/C12/G3/H8/ J11/K3/M11	I	ST	External Interrupt 2 input
EIC_EXTINT3	4/18/29	4/21/36	4/21/ 32/54/74	4/42/46/76/ 107/132	B3/B12/G2/H10/ H11/K4	I	ST	External Interrupt 3 input
EIC_EXTINT4	20	8/23/37	13/36/55/75	8/23/43/50/ 77/108/133	B4/B11/H2/H12/ J12/K5/K7	I	ST	External Interrupt 4 input
EIC_EXTINT5	21/32	9/24/40/56	14/37/59/92	9/24/51/59/80/ 84/134/136	B9/C6/E10/G8/ J1/K1/M2/M8	I	ST	External Interrupt 5 input
EIC_EXTINT6	8/22/33/45	10/25/41/57	15/39/60/93	10/25/53/60/ 85/81/137	C7/C9/D8/H9/ K2/M3/M9	I	ST	External Interrupt 6 input
EIC_EXTINT7	9/34/46	11/29/42/58	16/47/61/94	11/26/61/69/ 83/86/138	C5/D7/D10/F12/ L1/M4/M10	I	ST	External Interrupt 7 input
EIC_EXTINT8	-	12/30/61	17/48/97	17/27/62/ 70/87/141	A11/C8/E11/ H3/K8/L6	I	ST	External Interrupt 8 input
EIC_EXTINT9	10	13/31/44/62	22/49/63/98	20/33/63/71/ 88/94/142	B8/B10/E12/ G11/J4/L12/M7	I	ST	External Interrupt 9 input
EIC_EXTINT10	11/36	14/32/45/63	23/50/68/99	21/64/72/92/ 101/143	A10/B5/D12/ G12/J5/L7	I	ST	External Interrupt 10 input
EIC_EXTINT11	12/37	15/46/64	24/28/71/100	22/35/39/93/ 104/144	A4/A9/J3/ J9/K12/L8	I	ST	External Interrupt 11 input
EIC_EXTINT12	13	16/47	25/29/72/91	29/36/40/ 96/105/135	A3/A7/J2/ J10/K11/L9	I	ST	External Interrupt 12 input
EIC_EXTINT13	-	48	8/38/73	12/52/97/ 106/124	A2/B7/E3/ G10/L5	I	ST	External Interrupt 13 input
EIC_EXTINT14	1	1	1/40/58/9	1/13/54/ 82/125	C3/C4/G9/ L2/M5	I	ST	External Interrupt 14 input
EIC_EXTINT15	-	-	10/41/64	14/55/ 95/126	A8/F3/ F10/K6	I	ST	External Interrupt 15 input
EIC_NMI	42	53	88	121	D3	I	ST	Non-Maskable Interrupt input

Table 6-8. Ethernet MAC Signals
PIN NAME	PIN NUMBER					PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	PIN TYPE	FUNCTION TYPE	DESCRIPTION
ETH_COL	-	-	67	100	A5	I	ST/CMOS	Receiver Collision Detect
ETH_CRS	-	-	66	99	A6	I	ST	Receiver Carrier Sense
ETH_MDC	12/29/46	15/32/36/58	24/50/54/94	35/72/76/138	B12/D12/K12/L1	O	CMOS	Management data clock
ETH_MDIO	13/28/45	16/35/37/57	25/53/55/93	36/75/77/80/137	B11/C6/C12/K2/K11	I/O	ST/CMOS	Management data
ETH_REF_CLK	-	33	51	73	D11	I	ST	Reference Clock
ETH_RXD0	34	42	61	86	D7	I	ST	Ethernet Media Access Controller Receive data Rx[3:0]
ETH_RXD1	33	41	60	85	D8
ETH_RXD2	32	40	59	84	B9
ETH_RXD3	-	-	58	82	C4
ETH_RXDV	36	45	68	101	B5	I	ST	Receive Data Valid
ETH_RXER	-	44	63	94	B8	I	ST	Receive Data Error
ETH_RX_CLK	-	-	64	95	A8	I	ST	Receive Clock
ETH_TSUCOMP	42	53	88	121/127	D3/E2	O	CMOS	Time Stamp Unit Compensation
ETH_TXD0	-	47	72	105	A3	O	CMOS	Ethernet Media Access Controller Transmit data Tx[3:0]
ETH_TXD1	-	48	73	106	A2
ETH_TXD2	-	-	74	107	B3
ETH_TXD3	-	-	75	108	B4
ETH_TXEN	37	46	71	104	A4	O	CMOS	Transmit Enable
ETH_TXER	-	-	65	98	B6	O	CMOS	Transmit Error
ETH_TX_CLK	26	33	51	73	D11	I	ST	Transmit Clock

Table 6-9. Generic Clock Controller (GCLK) Signals
PIN NAME	PIN NUMBER					PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	PIN TYPE	FUNCTION TYPE	DESCRIPTION
GCLK_IO0	4/10	4/13	4/22	4/33	K4/L12	I	ST	External GCLK[7:0] pin Input clock source
GCLK_IO1	2/11	2/14	2/23	2/34	L3/L11
GCLK_IO2	26	33	51/91	8/73/135	D11/J2/K5
GCLK_IO3	27	34/56	52/92	9/74/136	C11/K1/M2
GCLK_IO4	28/45	35/57	53/93	10/75/137	C12/K2/M3
GCLK_IO5	29/46	36/58	54/94	11/76/138	B12/L1/M4
GCLK_IO6	-	37	12/55	16/77	B11/M6
GCLK_IO7	32	40	59	17/84	B9/L6

Table 6-10. Inter-IC Sound Controller (I²S) Signals
PIN NAME	PIN NUMBER					IOSET	PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	IOSET	PIN TYPE	FUNCTION TYPE	DESCRIPTION
SPI_IXS_FSYNC	45	57	93	137	K2	1	I/O	ST/CMOS	Frame Synchronization (LRCK)
	10	13	22	33	L12	2
	-	-	-	124	E3	3
SPI_IXS_SCK	-	63	99	143	J5	1	I/O	ST/CMOS	Serial Bit Clock
	12	15	24	35	K12	2
	-	-	-	125	C3	3
SPI_IXS_SDI	46	58	94	138	L1	1	I	ST	Serial Data Input for Receive Serializer
	13	16	25	36	K11	2
	-	-	-	127	E2	3
SPI_IXS_SDO	-	61	97	141	H3	1	O	CMOS	Serial Data Output for Transmit Serializer
	14	17	26	37	K10	2
	-	-	-	130	F2	3

Table 6-11. 32 kHz Oscillators Controller (OSC32KCTRL) Signals
PIN NAME	PIN NUMBER					PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	PIN TYPE	FUNCTION TYPE	DESCRIPTION
OSC32KCTRL_XIN32	17	20	31	45	J11	I	Analog	32.768 kHz oscillator input
OSC32KCTRL_XOUT32	18	21	32	46	H11	O	Analog	32.768 kHz oscillator output

Table 6-12. Oscillator Controller (OSCCTRL) Signals
PIN NAME	PIN NUMBER					PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	PIN TYPE	FUNCTION TYPE	DESCRIPTION
OSCCTRL_XIN	40	51	86	119	E1	I	Analog	Primary oscillator input
OSCCTRL_XOUT	41	52	87	120	F1	O	Analog	Primary oscillator output

Table 6-13. Parallel Capture Controller (PCC) Signals
PIN NAME	PIN NUMBER					IOSET	PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	IOSET	PIN TYPE	FUNCTION TYPE	DESCRIPTION
PCC_CLK	32	40	59	84	B9	1	I	ST	Parallel Capture Mode Clock
PCC_CLK	-	-	-	8	K5	2	I	ST	Parallel Capture Mode Clock
PCC_DATA0	27	34	52	74	C11	1	I/O	ST/CMOS	Parallel Capture Mode Data[13:0]
PCC_DATA0	-	-	-	9	M2	2
PCC_DATA1	28	35	53	75	C12	1
PCC_DATA1	-	-	-	10	M3	2
PCC_DATA2	29	36	54	76	B12	1
PCC_DATA2	-	-	-	11	M4	2
PCC_DATA3	33	29/41	47/60	69	F12	1
PCC_DATA3	-	-	-	17	L6	2
PCC_DATA4	34	30/42	48/61	70	E11	1
PCC_DATA4	-	-	-	20	M7	2
PCC_DATA5	36	31/45	49/68	71	E12	1
PCC_DATA5	-	-	-	21	L7	2
PCC_DATA6	37	32/46	50/71	72	D12	1
PCC_DATA6	-	-	-	22	L8	2
PCC_DATA7	26	33	51	73	D11	1
PCC_DATA7	-	-	-	29	L9	2
PCC_DATA8	-	-	64	95	A8	1
PCC_DATA8	-	-	-	41	H8	2
PCC_DATA9	-	-	65	98	B6	1
PCC_DATA9	-	-	-	42	H10	2
PCC_DATA10	-	-	66	99	A6	1
PCC_DATA10	-	-	-	43	J12	2
PCC_DATA11	-	-	67	100	A5	1
PCC_DATA11	-	-	-	64	G12	2
PCC_DATA12	-	-	-	107	B3	1
PCC_DATA12	-	-	74	80	C6	2
PCC_DATA13	-	-	-	108	B4	1
PCC_DATA13	-	-	75	81	C7	2
PCC_DEN1	11	14/37	23/55	34/77	B11/L11	1	I	ST	Parallel Capture Mode Enable 1
PCC_DEN1	-	-	-	132	G2	2	I	ST	Parallel Capture Mode Enable 1
PCC_DEN2	42	53	58/88	82/121	C4/D3	1	I	ST	Parallel Capture Mode Enable 2
PCC_DEN2	-	-	-	133	H2	2	I	ST	Parallel Capture Mode Enable 2

Table 6-14. Position Decoder (PDEC) Signals
PIN NAME	PIN NUMBER					IOSET	PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	IOSET	PIN TYPE	FUNCTION TYPE	DESCRIPTION
PDEC_QDI0	20	23	36	50	H12	1	I	ST	PDEC Inputs[2:0]
	-	29	47	69	F12	2
	20	23	36	8	K5	3
PDEC_QDI1	21	24	37	51	G8	1
	-	30	48	70	E11	2
	21	24	37	9	M2	3
PDEC_QDI2	-	31	49	71	E12	2
	-	-	38	52	G10	1
	22	25	39	10	M3	3

Table 6-15. PORTA through PORTD Signals
PIN NAME	PIN NUMBER					PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	PIN TYPE	FUNCTION TYPE	DESCRIPTION
PA00	1	1	1	1	L2	I/O	ST/CMOS	I/O Port A pins
PA01	2	2	2	2	L3
PA02	3	3	3	3	K3
PA03	4	4	4	4	K4
PA04	-	8	13	23	K7
PA05	-	9	14	24	M8
PA06	8	10	15	25	M9
PA07	9	11	16	26	M10
PA08	-	12	17	27	K8
PA09	10	13	22	33	L12
PA10	11	14	23	34	L11
PA11	12	15	24	35	K12
PA12	13	16	25	36	K11
PA13	-	-	8	12	L5
PA14	-	-	9	13	M5
PA15	-	-	10	14	K6
PA16	-	-	11	15	J6
PA17	-	-	12	16	M6
PA18	-	-	18	28	M11
PA19	-	-	21	32	L10
PA20	-	-	-	8	K5
PA21	-	-	-	9	M2
PA22	-	-	-	10	M3
PA23	-	-	-	11	M4
PA24	-	-	-	17	L6
PA25	-	-	-	20	M7
PA26	-	-	-	21	L7
PA27	-	-	-	22	L8
PA28	-	-	-	29	L9
PB00	14	17	26	37	K10	I/O	ST/CMOS	I/O Port B pins
PB01	15	18	27	38	K9
PB02	17	20	31	45	J11
PB03	18	21	32	46	H11
PB04	20	23	36	50	H12
PB05	21	24	37	51	G8
PB06	22	25	39	53	H9
PB07	-	29	47	69	F12
PB08	-	30	48	70	E11
PB09	-	31	49	71	E12
PB10	-	32	50	72	D12
PB11	-	-	28	39	J9
PB12	-	-	29	40	J10
PB13	-	-	38	52	G10
PB14	-	-	40	54	G9
PB15	-	-	41	55	F10
PB16	-	-	45	65	C10
PB17	-	-	46	68	F11
PB18	-	-	-	41	H8
PB19	-	-	-	42	H10
PB20	-	-	-	43	J12
PB21	-	-	-	59	E10
PB22	-	-	-	60	C9
PB23	-	-	-	61	D10
PB24	-	-	-	62	C8
PB25	-	-	-	63	G11
PB26	-	-	-	64	G12
PC00	26	33	51	73	D11	I/O	ST/CMOS	I/O Port C pins
PC01	27	34	52	74	C11
PC02	28	35	53	75	C12
PC03	29	36	54	76	B12
PC04	-	37	55	77	B11
PC05	32	40	59	84	B9
PC06	33	41	60	85	D8
PC07	34	42	61	86	D7
PC09	-	44	63	94	B8
PC10	36	45	68	101	B5
PC11	37	46	71	104	A4
PC12	-	47	72	105	A3
PC13	-	48	73	106	A2
PC14	-	-	58	82	C4
PC15	-	-	64	95	A8
PC16	-	-	65	98	B6
PC17	-	-	66	99	A6
PC18	-	-	67	100	A5
PC19	-	-	74	107	B3
PC20	-	-	75	108	B4
PC21	-	-	-	80	C6
PC22	-	-	-	81	C7
PC23	-	-	-	83	C5
PC24	-	-	-	87	A11
PC25	-	-	-	88	B10
PC26	-	-	-	92	A10
PC27	-	-	-	93	A9
PC28	-	-	-	96	A7
PC29	-	-	-	97	B7
PD00	40	51	86	119	E1	I/O	ST/CMOS	I/O Port D pins
PD01	41	52	87	120	F1
PD02	42	53	88	121	D3
PD05		56	92	136	K1
PD06	45	57	93	137	K2
PD07	46	58	94	138	L1
PD08	-	61	97	141	H3
PD09	-	62	98	142	J4
PD10	-	63	99	143	J5
PD11	-	64	100	144	J3
PD12	-	-	91	135	J2
PD13	-	-	-	124	E3
PD14	-	-	-	125	C3
PD15	-	-	-	126	F3
PD16	-	-	-	127	E2
PD17	-	-	-	130	F2
PD18	-	-	-	131	G3
PD19	-	-	-	132	G2
PD20	-	-	-	133	H2
PD21	-	-	-	134	J1

Table 6-16. Power (PWR) and Ground Signals
PIN NAME	PIN NUMBER					PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	PIN TYPE	FUNCTION TYPE	DESCRIPTION
AVDD	19	22	33	47	H7	PWR	Power	Positive supply for analog modules.
AVSS	16	19	30	44	F6	PWR	Power	Ground for analog modules.
VDDIO	7/23/30/39/48	7/26/38/50/60	7/20/34/42/ 56/69/85/96	7/19/31//48/ 56/66/78/ 90/102/118/ 129/140	D5/D6/D9/ E9/F4/F8/ G4/G7/H4/ H6/J7/J8	PWR	Power	Positive supply for I/O logic
VDDREG	24/35	28/43	44/62/83	58/89/116	E4/E7/F9	PWR	Power	Positive supply for CORE logic
VSS	6/25/31/38/47	6/27/39/49/59	6/19/35/43/57/ 70/80/84/95	6/18/30/44/ 49/57/67/79/ 91/113/117/ 128/139/204	A1/A12/D4/ E5/E6/E8/F5/ F7/G5/G6/ H5/M1/M12	PWR	Power	Ground for CORE, peripherals and I/O

Table 6-17. Peripheral Touch Controller (PTC) Signals
PIN NAME	PIN NUMBER					PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	PIN TYPE	FUNCTION TYPE	DESCRIPTION
PTC_DRV0	10	13	22	33	L12	I/O	ST/CMOS	Digital Output (X-line) & Analog I/O (Y-line)
PTC_DRV1	11	14	23	34	L11
PTC_DRV2	12	15	24	35	K12
PTC_DRV3	13	16	25	36	K11
PTC_DRV4	14	17	26	37	K10
PTC_DRV5	15	18	27	38	K9
PTC_DRV6	-	29	47	69	F12
PTC_DRV7	-	30	48	70	E11
PTC_DRV8	-	31	49	71	E12
PTC_DRV9	-	32	50	72	D12
PTC_DRV10	26	33	51	73	D11
PTC_DRV11	27	34	52	74	C11
PTC_DRV12	28	35	53	75	C12
PTC_DRV13	29	36	54	76	B12
PTC_DRV14	-	37	55	77	B11
PTC_DRV15	32	40	59	84	B9
PTC_DRV16	33	41	60	85	D8
PTC_DRV17	34	42	61	86	D7
PTC_DRV18	-	48	73	106	A2
PTC_DRV19	-	44	63	94	B8
PTC_DRV20	36	45	68	101	B5
PTC_DRV21	37	46	71	104	A4
PTC_DRV22	-	47	72	105	A3
PTC_DRV23	-	-	75	108	B4
PTC_DRV24	-	-	45	65	C10
PTC_DRV25	-	-	46	68	F11
PTC_DRV26	-	-	58	82	C4
PTC_DRV27	-	-	64	95	A8
PTC_DRV28	-	-	65	98	B6
PTC_DRV29	-	-	66	99	A6
PTC_DRV30	-	-	67	100	A5
PTC_DRV31	-	-	74	107	B3
PTC_ECI0	-	-	18	28	M11	I	Analog	External Capacitor Analog Input 0
PTC_ECI1	-	-	21	32	L10	I	Analog	External Capacitor Analog Input 1

Table 6-18. Real-Time Counter (RTC) Signals
PIN NAME	PIN NUMBER					PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	PIN TYPE	FUNCTION TYPE	DESCRIPTION
RTC_IN0	22	25	39	53	H9	I	ST	RTC security tamper input loops
RTC_IN1	15	18	27	38	K9
RTC_IN2	-	-	40	54	G9
RTC_IN3	-	-	41	55	F10
RTC_IN4	-	-	38	52	G10
RTC_IN5	-	-	-	42	H10
RTC_IN6	-	-	-	60	C9
RTC_IN7	-	-	-	62	C8
RTC_OUT0	21	24	37	51	G8	O	CMOS	RTC security tamper output loops
RTC_OUT1	14	17	26	37	K10
RTC_OUT2	-	-	28	39	J9
RTC_OUT3	-	-	29	40	J10
RTC_OUT4	-	-	45	65	C10
RTC_OUT5	-	-	-	41	H8
RTC_OUT6	-	-	-	59	E10
RTC_OUT7	-	-	-	61	D10

Table 6-19. Host Controller (SDMMC0 and SDMMC1) Signals
PIN NAME	PIN NUMBER					PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	PIN TYPE	FUNCTION TYPE	DESCRIPTION
SDMMC0_SDCD	11/13/36	14/16/37/45	23/25/55/68/91	34/36/135	L11/K11/J2	I	ST	SD Host Controller 0 Card Detect (10K-100K Pull-up required)
SDMMC0_SDCK	32	40/63	59/99	143	J5	O	CMOS	SD Host Controller 0 Clock
SDMMC0_SDCMD	33/45	29/41/57	47/60/93	137	K2	I/O	ST/CMOS	SD Host Controller 0 Command (10K-100K Pull-up required)
SDMMC0_SDDAT0	34/46	32/42/58	50/61/94	138	L1	I/O	ST/CMOS	SD Host Controller 0 DATA0 (10K-100K Pullup required)
SDMMC0_SDDAT1	26	33/64	51/100	144	J3			SD Host Controller 0 DATA1 (10K-100K Pullup required)
SDMMC0_SDDAT2	27	34/61	52/97	141	H3			SD Host Controller 0 DATA2 (10K-100K Pullup required)
SDMMC0_SDDAT3	28	35/62	53/98	142	J4			SD Host Controller 0 DATA3 (10K-100K Pullup required)
SDMMC0_SDWP	14/29	17/36/56	26/54/92	37/136	K10/K1	I	ST	SD Host Controller 0 Write Protect (10K-100K Pull-up required)
SDMMC1_SDCD	-	37	55	77	B11	I	ST	SD Host Controller 1 Card Detect (10K-100K Pull-up required)
SDMMC1_SDCK	-	40	59	84	B9	O	CMOS	SD Host Controller 1 Clock
SDMMC1_SDCMD	-	29	47	69	F12	I/O	ST/CMOS	SD Host Controller 1 Command (10K-100K Pull-up required)
SDMMC1_SDDAT0	-	32	50	72	D12	I/O	ST/CMOS	SD Host Controller 1 DATA0 (10K-100K Pullup required)
SDMMC1_SDDAT1	-	33	51	73	D11			SD Host Controller 1 DATA1 (10K-100K Pullup required)
SDMMC1_SDDAT2	-	34	52	74	C11			SD Host Controller 1 DATA2 (10K-100K Pullup required)
SDMMC1_SDDAT3	-	35	53	75	C12			SD Host Controller 1 DATA3 (10K-100K Pullup required)
SDMMC1_SDWP	-	36	54	76	B12	I	ST	SD Host Controller 1 Write Protect (10K-100K Pull-up required)

Table 6-20. Serial Communication Interface (SERCOM) Signals
PIN NAME	PIN NUMBER					IOSET	PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 TQFP	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	IOSET	PIN TYPE	FUNCTION TYPE	DESCRIPTION
SERCOM0_PAD0	36	45	68	101	B5	1	I/O	ST/CMOS	UART0_RxD, TxD / SPI0_DI,DO / I2C0_SDA
	-	-	-	130	F2	2
	45	57	93	137	K2	3
SERCOM0_PAD1	37	46	71	104	A4	1			UART0_RxD,XCK / SPI0_DI, SCK / I2C0_SCL
	-	-	-	131	G3	2
	46	58	94	138	L1	3
SERCOM0_PAD2	-	47	72	105	A3	1			UART0_RxD, RTS, TE / SPI0_DI, S̅S̅ / I2C0_SDA_OUT
	-	-	-	132	G2	2
	1	56	92	136	K1	3
SERCOM0_PAD3	-	48	73	106	A2	1			UART0_RxD, CTS / SPI0_DI,DO / I2C0_SCL_OUT
	-	-	-	133	H2	2
	2	-	91	135	J2	3
SERCOM1_PAD0	-	61	97	141	H3	1	I/O	ST/CMOS	UART1_RxD, TxD / SPI1_DI,DO / I2C1_SDA
SERCOM1_PAD0	1	-	-	124	E3	2			UART1_RxD, TxD / SPI1_DI,DO / I2C1_SDA
SERCOM1_PAD1	-	62	98	142	J4	1			UART1_RxD,XCK / SPI1_DI, SCK / I2C1_SCL
SERCOM1_PAD1	2	-	-	125	C3	2			UART1_RxD,XCK / SPI1_DI, SCK / I2C1_SCL
SERCOM1_PAD2	-	63	99	143	J5	1			UART1_RxD, RTS,TE / SPI1_DI, S̅S̅ / I2C1_SDA_OUT
SERCOM1_PAD2	45	-	-	126	F3	2			UART1_RxD, RTS,TE / SPI1_DI, S̅S̅ / I2C1_SDA_OUT
SERCOM1_PAD3	-	64	100	144	J3	1			UART1_RxD, CTS / SPI1_DI,DO / I2C1_SCL_OUT
SERCOM1_PAD3	46	-	-	127	E2	2			UART1_RxD, CTS / SPI1_DI,DO / I2C1_SCL_OUT
SERCOM2_PAD0	37	46	71	104	A4	1	I/O	ST/CMOS	UART2_RxD, TxD / SPI2_DI,DO / I2C2_SDA
	-	-	64	95	A8	2
	37	46	71	80	C6	3
	33	41	60	85	D8	4
SERCOM2_PAD1	36	45	68	101	B5	1			UART2_RxD,XCK / SPI2_DI, SCK / I2C2_SCL
	-	-	65	98	B6	2
	36	45	68	81	C7	3
	34	42	61	86	D7	4
SERCOM2_PAD2	-	47	72	105	A3	1			UART2_RxD, RTS, TE / SPI2_DI, S̅S̅ / I2C2_SDA_OUT
	-	-	66	99	A6	2
	32	40	58	82	C4	3
	-	44	63	94	B8	4
SERCOM2_PAD3	-	48	73	106	A2	1			UART2_RxD, CTS / SPI2_DI,DO / I2C2_SCL_OUT
	-	-	67	100	A5	2
	28	-	-	83	C5	3
	-	-	-	92	A10	4
SERCOM3_PAD0	28	35	53	75	C12	1	I/O	ST/CMOS	UART3_RxD, TxD / SPI3_DI,DO / I2C3_SDA
	-	-	45	65	C10	2
	-	-	-	59	E10	3
	34	42	61	86	D7	4
SERCOM3_PAD1	29	36	54	76	B12	1			UART3_RxD,XCK / SPI3_DI, SCK / I2C3_SCL
	-	-	46	68	F11	2
	-	-	-	60	C9	3
	33	41	60	85	D8	4
SERCOM3_PAD2	-	37	55	77	B11	1			UART3_RxD, RTS,TE / SPI3_DI, S̅S̅ / I2C3_SDA_OUT
	-	29	47	69	F12	2
	-	-	-	61	D10	3
	27	34/44	52/63	94	B8	4
SERCOM3_PAD3	32	40	59	84	B9	1			UART3_RxD, CTS / SPI3_DI,DO / I2C3_SCL_OUT
	-	30	48	70	E11	2
	-	-	-	62	C8	3
	26	33	51/64	95	A8	4
SERCOM4_PAD0	-	31	49	71	E12	1	I/O	ST/CMOS	UART4_RxD, TxD / SPI4_DI,DO / I2C4_SDA
	20	-	-	50	H12	2
	-	-	29	40	J10	3
	-	32	50	72	D12	4
SERCOM4_PAD1	-	32	50	72	D12	1			UART4_RxD,XCK / SPI4_DI, SCK / I2C4_SCL
	21	-	-	51	G8	2
	-	-	-	41	H8	3
	-	31	49	71	E12	4
SERCOM4_PAD2	26	33	51	73	D11	1			UART4_RxD, RTS,TE / SPI4_DI, S̅S̅ / I2C4_SDA_OUT
	11	-	38	52	G10	2
	-	-	-	42	H10	3
	-	29	47	69	F12	4
SERCOM4_PAD3	27	34	52	74	C11	1			UART4_RxD, CTS / SPI4_DI,DO / I2C4_SCL_OUT
	22	-	-	53	H9	2
	-	-	-	43	J12	3
	-	30	48	70	E11	4
SERCOM5_PAD0	12	15	24	35	K12	1	I/O	ST/CMOS	UART5_RxD, TxD / SPI5_DI,DO / I2C5_SDA
	-	-	8	12	L5	2
	-	-	-	17	L6	3
	-	9	14	24	M8	4
SERCOM5_PAD1	13	16	25	36	K11	1			UART5_RxD,XCK / SPI5_DI, SCK / I2C5_SCL
	-	-	9	13	M5	2
	-	-	-	20	M7	3
	8	10	15	25	M9	4
SERCOM5_PAD2	14	17	26	37	K10	1			UART5_RxD, RTS,TE / SPI5_DI, S̅S̅ / I2C5_SDA_OUT
	-	-	10	14	K6	2
	-	-	-	21	L7	3
	9	11	16	26	M10	4
SERCOM5_PAD3	15	18	27	38	K9	1			UART5_RxD, CTS / SPI5_DI,DO / I2C5_SCL_OUT
	-	-	11	15	J6	2
	-	-	-	22	L8	3
	-	12	17	27	K8	4
SERCOM6_PAD0	-	11	16	26	M10	1	I/O	ST/CMOS	UART6_RxD, TxD / SPI6_DI,DO / I2C6_SDA
	-	1	1	1	L2	2
	-	-	18	28	M11	3
SERCOM6_PAD1	-	12	17	27	K8	1			UART6_RxD,XCK / SPI6_DI, SCK / I2C6_SCL
	-	2	2	2	L3	2
	-	-	-	29	L9	3
SERCOM6_PAD2	-	13	22	33	L12	1			UART6_RxD, RTS,TE / SPI6_DI, S̅S̅ / I2C6_SDA_OUT
	-	3	3	3	K3	2
	-	-	21	32	L10	3
SERCOM6_PAD3	-	14	23	34	L11	1			UART6_RxD, CTS / SPI6_DI,DO / I2C6_SCL_OUT
	-	4	4	4	K4	2
	-	13	22	33	L12	3
SERCOM7_PAD0	-	2	2	2	L3	1	I/O	ST/CMOS	UART7_RxD, TxD / SPI7_DI,DO / I2C7_SDA
	-	-	-	9	M2	2
	-	16	25	36	K11	3
	-	-	-	41	H8	4
SERCOM7_PAD1	-	8	13	23	K7	1			UART7_RxD,XCK / SPI7_DI, SCK / I2C7_SCL
	-	-	-	8	K5	2
	-	15	24	35	K12	3
	-	-	29	40	J10	4
SERCOM7_PAD2	-	9	14	24	M8	1			UART7_RxD, RTS,TE / SPI7_DI, S̅S̅ / I2C7_SDA_OUT
	-	-	-	10	M3	2
	-	17	26	37	K10	3
	-	-	-	42	H10	4
SERCOM7_PAD3	-	10	15	25	M9	1			UART7_RxD, CTS / SPI7_DI,DO / I2C7_SCL_OUT
	-	-	-	11	M4	2
	-	18	27	38	K9	3
	-	-	-	43	J12	4

Table 6-21. Quad Serial Peripheral Interface (QSPI/SQI) Signals
PIN NAME	PIN NUMBER					PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	PIN TYPE	FUNCTION TYPE	DESCRIPTION
SQI_CLK	33	41/63	60/99	143	J5	O	CMOS	Quad SPI Clock
SQI_CS0	27/45	34/57	52/93	137	K2	O	CMOS	Quad SPI Chip Select 0
SQI_CS1	26	33/56	51/92	136	K1			Quad SPI Chip Select 1
SQI_CS2	11	14	23	34	L11			Quad SPI Chip Select 2
SQI_CS3	-	-	91	135	J2			Quad SPI Chip Select 3
SQI_DATA0	28/34/46	35/42/58	52/61/94	138	L1	I/O	ST/CMOS	Quad SPI Data 0 I/O
SQI_DATA1	-	64	100	144	J3			Quad SPI Data 1 I/O
SQI_DATA2	29	36/61	54/97	141	H3			Quad SPI Data 2 I/O
SQI_DATA3	32	40/62	59/98	142	J4			Quad SPI Data 3 I/O

Table 6-22. Supply Controller (SUPC) Signals
PIN NAME	PIN NUMBER					PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	PIN TYPE	FUNCTION TYPE	DESCRIPTION
SUPC_BKOUT0	21	24	37	51	G8	O	CMOS	SUPC Backup Output 0
SUPC_BKOUT1	-	-	38	52	G10	O	CMOS	SUPC Backup Output 1

Table 6-23. Timer Counter for Control (TCC) Signals
PIN NAME	PIN NUMBER					IOSET	PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	IOSET	PIN TYPE	FUNCTION TYPE	DESCRIPTION
TCC0_WO0	20	23	36	50	H12	1	I/O	ST/CMOS	TCC0 Waveform Outputs/Input Counter/Capture
TCC0_WO0	-	32	50	72	D12	2
TCC0_WO1	21	24	37	51	G8	1
TCC0_WO1	26	33	51	73	D11	2
TCC0_WO2	-	-	38	52	G10	1
TCC0_WO2	27	34	52	74	C11	2
TCC0_WO3	22	25	39	53	H9	1
TCC0_WO3	28	35	53	75	C12	2
TCC0_WO4	-	-	40	54	G9	1
TCC0_WO4	29	36	54	76	B12	2
TCC0_WO5	-	-	41	55	F10	1
TCC0_WO5	-	37	55	77	B11	2
TCC0_WO6	-	-	-	59	E10	1
TCC0_WO6	-	-	-	80	C6	2
TCC0_WO7	-	-	-	60	C9	1
TCC0_WO7	-	-	-	81	C7	2
TCC1_WO0	-	-	64	95	A8	1	I/O	ST/CMOS	TCC1 Waveform Outputs/Input Counter/Capture
TCC1_WO0	32	40	59	84	B9	2
TCC1_WO1	-		65	98	B6	1
TCC1_WO1	33	41	60	85	D8	2
TCC1_WO2	-	-	66	99	A6	1
TCC1_WO2	34	42	61	86	D7	2
TCC1_WO3	-	-	67	100	A5	1
TCC1_WO3	-	44	63	94	B8	2
TCC1_WO4	-	-	74	107	B3	1
TCC1_WO4	-	-	64	95	A8	2
TCC1_WO5	-	-	75	108	B4	1
TCC1_WO5	36	45	68	101	B5	2
TCC1_WO6	-	-		96	A7	1
TCC1_WO6	37	46	71	104	A4	2
TCC1_WO7	-	-		97	B7	1
TCC1_WO7	-	47	72	105	A3	2
TCC2_WO0	1	1	1	1	L2	1	I/O	ST/CMOS	TCC2 Waveform Outputs/Input Counter/Capture
TCC2_WO0	1	1/56	1/92	136	K1	2
TCC2_WO1	-		91	135	J2	1
TCC2_WO1	37/45	46/57	71/93	137	K2	2
TCC2_WO2	-	64	100	144	J3	1
TCC2_WO2	36/46	45/58	68/94	138	L1	2
TCC2_WO3	2	2	2	2	L3	1
TCC2_WO3	2	2/61	2/97	141	H3	2
TCC2_WO4	45	57	93	137	K2	1
TCC2_WO4	45	57/62	93/98	142	J4	2
TCC2_WO5	46	58	94	138	L1	1
TCC2_WO5	46	58/63	94/99	143	J5	2
TCC2_WO6	-	-	-	124	E3	1
TCC2_WO6	-	64	100	144	J3	2
TCC2_WO7	-	-	-	125	C3	1
TCC2_WO7	-	-	91	135	J2	2
TCC3_WO0	-	8	13	23	K7	1	I/O	ST/CMOS	TCC3 Waveform Outputs/Input Counter/Capture
	10	13	22	33	L12	2
	10	13	22	-	-	3
TCC3_WO1	-	9	14	24	M8	1
	-	14	23	34	L11	2
	11	14	23	-	-	3
TCC3_WO2	-	10	15	25	M9	1
	12	15	24	35	K12	2
	12	15	24	-	-	3
TCC3_WO3	-	11	16	26	M10	1
	13	16	25	36	K11	2
	13	16	25	-	-	3
TCC3_WO4	-	12	17	27	K8	1
	14	17	26	37	K10	2
	14	17	26	-	-	3
TCC3_WO5	-	-	18	28	M11	1
	15	18	27	38	K9	2
	15	18	27	-	-	3
TCC3_WO6	-	-		29	L9	1
	-	-	28	39	J9	2
	8	10	15	-	-	3
TCC3_WO7	-	-	21	32	L10	1
	-	-	29	40	J10	2
	9	11	16	-	-	3
TCC4_WO0	12	15	24	35	K12	1	I/O	ST/CMOS	TCC4 Waveform Outputs/Input Counter/Capture
	-	-	8	12	L5	2
	-	-		8	K5	3
	-	-	29	40	J10	4
TCC4_WO1	13	16	25	36	K11	1
	-	-	9	13	M5	2
	-	-	-	9	M2	3
	-	-	-	41	H8	4
TCC5_WO0	14	17	26	37	K10	1	I/O	ST/CMOS	TCC5 Waveform Outputs/Input Counter/Capture
	-	-	10	14	K6	2
	-	-	-	10	M3	3
	-	-	-	42	H10	4
TCC5_WO1	15	18	27	38	K9	1
	-	-	11	15	J6	2
	-	-	-	11	M4	3
	-	-	-	43	J12	4
TCC6_WO0	-	34	52	74	C11	1	I/O	ST/CMOS	TCC6 Waveform Outputs/Input Counter/Capture
	-	-	45	65	C10	2
	-	-	-	61	D10	3
TCC6_WO1	-	35	53	75	C12	1
	-	-	46	68	F11	2
	-	-	-	62	C8	3
TCC7_WO0	-	29	47	69	F12	1	I/O	ST/CMOS	TCC7 Waveform Outputs/Input Counter/Capture
	-	36	54	76	B12	2
	-	-	-	63	G11	3
TCC7_WO1	-	30	48	70	E11	1
	-	37	55	77	B11	2
	-	-	-	64	G12	3

Table 6-24. Full-Speed Universal Serial Bus (USB) Signals
PIN NAME	PIN NUMBER					IOSET	PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	48 VQFN	64 TQFP	100 TQFP	144 TQFP	144 TFBGA	IOSET	PIN TYPE	FUNCTION TYPE	DESCRIPTION
USB_DM	43	54	89	122	G1	1	I/O	Analog	USB FS D- differential data line
USB_DP	44	55	90	123	H1	1	I/O	Analog	USB FS D+ differential data line
USB_SOF_1KHZ	42	53	88	121	D3	1	O	CMOS	USB FS Start of Frame
USB_SOF_1KHZ	27	34	52	74	C11	2	O	CMOS	USB FS Start of Frame

Table 6-25. High-Speed Universal Serial Bus (USBHS) Signals
PIN NAME	PIN NUMBER			PIN TYPE	FUNCTION TYPE	DESCRIPTION
PIN NAME	100 TQFP	144 TQFP	144 TFBGA	PIN TYPE	FUNCTION TYPE	DESCRIPTION
USBHS_USB0ID	78	111	C2	O	CMOS	USB HS ID Detect
USBHS_USB0PN	76	109	B1	I/O	Analog	USB HS D- differential data line
USBHS_USB0PP	77	110	C1	I/O	Analog	USB HS D+ differential data line
USBHS_USBRBIAS	82	115	D2	I	Analog	270Ω ±1% resistor to AGND
USBHS_VBUS	81	114	D1	I	Analog	USB HS Bus Power Monitor