Jump to main content
32-bit MCU with TrustZone and Integrated Security
Up to 2 MB Live-Update Flash and 512 KB SRAM with Hardware Security Module (HSM) for Secure Connectivity Applications
1 Configuration Summary
2 Guidelines for Getting Started
2.1 Basic Connection Requirements
2.2 Decoupling Capacitors
2.3 External Reset (RESET) Pin
2.4 Debugging or Programming Pins
2.5 JTAG
2.6 Trace
2.7 External Oscillator Pins
2.8 Unused I/Os
2.9 Considerations When Interfacing to Remotely Powered Circuits
2.10 Designing for High-Speed Peripherals
3 Ordering Information
4 Block Diagram
5 Package and Pinout
5.1 48-Pin Packages
5.2 64-Pin Packages
5.3 100-Pin Packages
5.4 144-Pin Packages
6 Signal Description
7 Power Supplies and Startup Considerations
7.1 Power Domain Overview
7.2 Power Domain Constraints
7.3 Power-Up
7.4 Power-on Reset and Brown-out Reset
7.5 Analog Peripherals Considerations
7.6 Device Startup
8 Product Mapping
8.1 Code Address Space
8.2 SRAM Address Space
8.3 Peripheral Address Space
8.4 External RAM Address Space
8.5 Peripheral Bus A Address Map
8.6 Peripheral Bus B Address Map
8.7 Peripheral Bus C Address Map
8.8 Peripheral Bus AHB Address Map
8.9 Flash CFM Configuration Address Map
9 Peripherals
9.1 Register Description
10 Processor and Architecture
10.1 Overview
10.2 Nested Vectored Interrupt Controller
10.3 High-Speed Bus
11 Memories
11.1 Embedded Memories
11.2 Physical Memory Map
11.3 SRAM Memory Configuration
11.4 PFM Error Correction
11.5 Configuration Flash Memory (CFM)
11.6 BFM Integrity Check
11.7 CAL OTP Configuration
11.8 Unique ID (UID)
12 Hardware Security Module (HSM)
12.1 Features
12.2 Performance
13 Multi-Channel RAM Controller (MCRAMC)
13.1 Overview
13.2 Features
13.3 Block Diagram
13.4 Functional Description
13.5 Register Summary
14 Cortex-M Cache Controller (CMCC)
14.1 Overview
14.2 Features
14.3 Block Diagram
14.4 Peripheral Dependencies
14.5 Functional Description
14.6 DEBUG Mode
14.7 RAM Properties
14.8 Register Summary
15 Implementation Defined Attribution Unit (IDAU)
15.1 Overview
15.2 IDAU Region Types
15.3 Main Region Types
15.4 Splittable Main Regions
15.5 Exempt_B Layout
15.6 SECNNONSEC_B Layout
15.7 IDAU Regions IDS
15.8 IDAU Regions Configuration
15.9 Configuration Write Lock
15.10 Linked IDAU Regions
15.11 IDAU Register Summary
16 Peripheral Access Controller (PAC)
16.1 Overview
16.2 Features
16.3 Block Diagram
16.4 Peripheral Dependencies
16.5 Functional Description
16.6 Register Summary
17 Device Service Unit (DSU)
17.1 Overview
17.2 Features
17.3 PIC32CK SG/GC DSU Block Diagram
17.4 Signal Description
17.5 Peripheral Dependencies
17.6 Indexing
17.7 Debug Operation
17.8 Multi-Processor Support
17.9 Programming
17.10 Security Enforcement
17.11 Device Identification
17.12 Functional Description
17.13 Register Summary
17.14 DATA Register Summary in MBIST Mode
18 Clock Distribution System
18.1 Clock Distribution
18.2 Synchronous and Asynchronous Clocks
18.3 Register Synchronization
18.4 Enabling a Peripheral
18.5 On Demand Clock Requests
18.6 Power Consumption Versus Speed
18.7 Clocks after Reset
19 Oscillator Controller (OSCCTRL)
19.1 Overview
19.2 Features
19.3 OSCCTRL Block Diagram
19.4 Signal Descriptions
19.5 Peripheral Dependencies
19.6 Functional Description
19.7 Register Summary
20 Generic Clock Controller (GCLK)
20.1 Overview
20.2 Features
20.3 Block Diagram
20.4 Signal Description
20.5 Peripheral Dependencies
20.6 Functional Description
20.7 Register Summary
21 Main Clock (MCLK)
21.1 Overview
21.2 Features
21.3 Block Diagram
21.4 Peripheral Dependencies
21.5 Functional Description
21.6 Register Summary
22 32 KHz Oscillators Controller (OSC32KCTRL)
22.1 Overview
22.2 Features
22.3 Block Diagram
22.4 Signal Description
22.5 Peripheral Dependencies
22.6 Functional Description
22.7 Register Summary
23 Watchdog Timer (WDT)
23.1 Overview
23.2 Features
23.3 Block Diagram
23.4 Peripheral Dependencies
23.5 Functional Description
23.6 Register Summary
24 Frequency Meter (FREQM)
24.1 Overview
24.2 Features
24.3 Block Diagram
24.4 Signal Description
24.5 Peripheral Dependencies
24.6 Clocks
24.7 Functional Description
24.8 Register Summary
25 Real-Time Counter (RTC)
25.1 Overview
25.2 Features
25.3 Block Diagram
25.4 Signal Description
25.5 Peripheral Dependencies
25.6 Functional Description
25.7 Register Summary - 32-bit Counter Mode
25.8 Register Summary - 16-bit Counter Mode
25.9 Register Summary Clock/Calendar Mode
26 Direct Memory Access Controller (DMAC)
26.1 Overview
26.2 Features
26.3 Block Diagram
26.4 Peripheral Dependencies
26.5 Indexing
26.6 DMA Event/Trigger Mapping
26.7 Applications
26.8 Module Description
26.9 Register Summary
26.10 Channelk Register Summary, k = 0,1,...,11
27 Supply Controller (SUPC)
27.1 Overview
27.2 Features
27.3 Block Diagram
27.4 Signals Description
27.5 Peripheral Dependencies
27.6 Functional Description
27.7 Register Summary
28 Power Manager (PM)
28.1 Overview
28.2 Features
28.3 Block Diagram
28.4 Peripheral Dependencies
28.5 Functional Description
28.6 Register Summary
29 Reset Controller (RSTC)
29.1 Overview
29.2 Features
29.3 Block Diagram
29.4 Signals Description
29.5 Peripheral Dependencies
29.6 Functional Description
29.7 Register Summary
30 External Interrupt Controller (EIC)
30.1 Overview
30.2 Features
30.3 Block Diagram
30.4 Signal Description
30.5 Peripheral Dependencies
30.6 Functional Description
30.7 Register Summary
31 Non-Volatile Memory Controller (NVMCTRL)
31.1 Block Diagram
31.2 Flash Controller, Write
31.3 Flash Controller, Read
32 Ethernet Media Access Controller (ETH)
32.1 Overview
32.2 Features
32.3 Block Diagram
32.4 Signal Interface
32.5 Peripheral Dependencies
32.6 Functional Description
32.7 Programming Interface
32.8 Register Summary
33 Event System (EVSYS)
33.1 Overview
33.2 Features
33.3 Block Diagram
33.4 Peripheral Dependencies
33.5 Power Management
33.6 Clocks
33.7 Functional Description
33.8 Register Summary
34 I/O Pin Controller (PORT)
34.1 Overview
34.2 Features
34.3 Block Diagram
34.4 Signal Description
34.5 Peripheral Dependencies
34.6 I/O Lines
34.7 Clocks
34.8 CPU AHB Bus
34.9 Power Management
34.10 Debug Operation
34.11 Functional Description
34.12 Register Summary
35 Serial Communication Interface (SERCOM)
35.1 Overview
35.2 Features
35.3 Block Diagram
35.4 Peripheral Dependencies
35.5 Functional Description
35.6 SERCOM USART - SERCOM Synchronous and Asynchronous Receiver and Transmitter
35.7 SERCOM Serial Peripheral Interface (SPI)
35.8 SERCOM I2C
36 Serial Quad Interface (SQI)
36.1 Overview
36.2 Features
36.3 Block Diagram
36.4 Peripheral Dependencies
36.5 Functional Description
36.6 Register Summary
37 Universal Serial Bus Hi-Speed (USBHS)
37.1 Overview
37.2 Features
37.3 Block Diagram
37.4 Signal Description
37.5 Peripheral Dependencies
37.6 Functional Description
37.7 Register Summary: USB Common Registers
37.8 Register Summary: USB Endpoint0 Common Registers
37.9 Register Summary: USB Host Mode Only Registers
37.10 Register Summary: Home Mode Endpoint0 Registers
37.11 Register Summary: USB Host Mode Endpoint1-7 Registers
37.12 Register Summary: Device Mode Only Common Registers
37.13 Register Summary: Device Mode Endpoint0 Registers
37.14 Register Summary: Device Mode Endpoint1-7 Registers
38 Full-Speed Universal Serial Bus (USBFS)
38.1 Overview
38.2 Features
38.3 USB Block Diagram
38.4 Signal Description
38.5 Peripheral Dependencies
38.6 Functional Description
38.7 Communication Device Host Register Summary
38.8 Device Registers - Common -Register Summary
38.9 Device Endpoint Register Summary
38.10 Endpoint Descriptor Structure
38.11 Device Endpoint RAM Register Summary
38.12 Host Registers - Common - Register Summary
38.13 Host Registers - Pipe - Register Summary
38.14 Pipe Descriptor Structure
38.15 Host Registers - Pipe RAM - Register Summary
39 Controller Area Network (CAN)
39.1 Overview
39.2 Features
39.3 Block Diagram
39.4 Signal Description
39.5 Peripheral Dependencies
39.6 Functional Description
39.7 Register Summary
40 External Bus Interface (EBI)
40.1 Overview
40.2 Features
40.3 EBI Block Diagram
40.4 I/O Lines Description
40.5 Application Example
40.6 Peripheral Dependencies
40.7 Functional Description
40.8 Register Summary
41 SD/MMC Host Controller (SDHC)
41.1 Overview
41.2 Features
41.3 Block Diagram
41.4 Connection Diagram
41.5 Signal Description
41.6 Peripheral Dependencies
41.7 Functional Description
41.8 Register Summary
42 True Random Number Generator (TRNG)
42.1 Overview
42.2 Features
42.3 Block Diagram
42.4 Peripheral Dependencies
42.5 Clocks
42.6 Functional Description
42.7 Register Summary
43 Configurable Custom Logic (CCL)
43.1 Overview
43.2 Features
43.3 Block Diagram
43.4 Signal Description
43.5 Peripheral Dependencies
43.6 Functional Description
43.7 Register Summary
44 Analog-to-Digital Converter (ADC)
44.1 Overview
44.2 Features
44.3 Block Diagram
44.4 Signal Description
44.5 Peripheral Dependencies
44.6 Functional Description
44.7 Register Summary
45 Analog Comparators (AC)
45.1 Overview
45.2 Features
45.3 Block Diagram
45.4 Analog Connections
45.5 Peripheral Dependencies
45.6 Functional Description
45.7 Register Summary
46 Position Decoder (PDEC)
46.1 Overview
46.2 Features
46.3 Block Diagram
46.4 Signal Description
46.5 Peripheral Dependencies
46.6 Functional Description
46.7 Register Summary
47 Parallel Capture Controller (PCC)
47.1 Overview
47.2 Features
47.3 Block Diagram
47.4 Signal Description
47.5 Peripheral Dependencies
47.6 Functional Description
47.7 Register Summary
48 Timer/Counter for Control Applications (TCC)
48.1 Overview
48.2 Features
48.3 Block Diagram
48.4 Signal Description
48.5 Peripheral Dependencies
48.6 Functional Description
48.7 Register Summary
49 TrustRAM (TRAM)
49.1 Overview
49.2 Features
49.3 Block Diagram
49.4 Peripheral Dependencies
49.5 Functional Description
49.6 Register Summary
50 Peripheral Touch Controller (PTC)
50.1 Overview
50.2 Features
50.3 Block Diagram
50.4 Signal Description
50.5 Peripheral Dependencies
50.6 Functional Description
51 Inter-IC Sound Controller (I2S)
51.1 Overview
51.2 Features
51.3 Block Diagram
51.4 Peripheral Dependencies
51.5 Functional Description
51.6 Register Summary
52 Electrical Characteristics (85°C)
52.1 Absolute Maximum Electrical Characteristics
52.2 CPU Electrical Characteristics
52.3 Power Supply
52.4 MCU Active Power
52.5 MCU Idle Power
52.6 MCU Standby Power
52.7 MCU Hibernate Power
52.8 MCU Backup Power
52.9 MCU Off Power
52.10 Wake-Up Timing
52.11 Peripheral Active Power
52.12 I/O Pin Electrical Specifications
52.13 Internal Voltage Reference Electrical Specifications
52.14 Maximum Clock Frequencies
52.15 External Oscillator (XOSC) Electrical Specifications
52.16 External 32.768 kHz Oscillator (XOSC32) Electrical Specifications
52.17 Low Power Internal 32kHz RC Oscillator (OSCULP32K) Electrical Specifications
52.18 DFLL/PLL Electrical Specifications
52.19 Analog-to-Digital Converter (ADC) Electrical Specifications
52.20 Comparator Electrical Specifications
52.21 Peripheral Touch Controller (PTC) Electrical Specifications
52.22 Serial Peripheral Interface (SPI) Electrical Specifications
52.23 UART Electrical Specifications
52.24 I2S Electrical Specifications
52.25 I2C Electrical Specifications
52.26 SQI/QSPI Electrical Specifications
52.27 Controller Area Network (CAN) Electrical Specifications
52.28 Timer Counter for Control Applications (TCC) Electrical Specifications
52.29 Universal Serial Bus (USB) Electrical Specifications
52.30 Parallel Capture Controller (PCC) Electrical Specifications
52.31 Non-Volatile Memory Controller (NVM) Electrical Specifications
52.32 Ethernet MAC (ETH) Electrical Specifications
52.33 Frequency Meter (FREQM) Electrical Specifications
52.34 True Random Number Generator (TRNG) Electrical Specifications
52.35 Position Decoder (PDEC) Electrical Specifications
52.36 SD/MMC Host Controller (SDHC) Electrical Specifications
52.37 External Bus Interface (EBI) Electrical Specifications
52.38 JTAG Electrical Specifications
52.39 SWD 2-Wire Electrical Specifications
53 Extended Temperature Electrical Characteristics (125°C)
53.1 CPU Electrical Characteristics
53.2 I/O Pin AC/DC Electrical Specifications
53.3 Maximum Clock Frequencies Electrical Specifications
53.4 ADC Electrical Specifications
53.5 Analog Comparator (AC) Electrical Specifications
53.6 NVM Block (Flash, Data Flash, NVM Configuration Rows) Electrical Specifications
54 Packaging Information
54.1 Package Marking Information
54.2 Package Drawings
54.3 Soldering Profile
55 Schematic Checklist
55.1 Introduction
56 Common Conventions
56.1 Numerical Notation
56.2 Memory Size and Type
56.3 Frequency and Time
56.4 Registers and Bits
57 Acronyms and Abbreviations
58 Revision History
59 Product Identification System
Microchip Information
Trademarks
Legal Notice
Microchip Devices Code Protection Feature