13.1 Overview

The MCRAMC provides memory controller functions as well as ECC and fault injection for the System RAM (DRM).

The memory controller provides up to 8 AHB ports which provide access the system RAM. Each port is guaranteed 100% bandwidth to the entire system RAM. However, there may be a latency penalties if more than one port attempts to access the same memory bank. The CPU master has exclusive access to AHB port 0 which is configured to a higher priority than other AHB ports. This configuration provides the CPU with the lowest overall latency to the system memory.

The memory controller also provides ECC and fault injection. The user can optional enable/disable ECC correction of read data. ECC values are always calculated and stored for writes. Both SEC and DED errors are logged and each event can generate an interrupt. On a SEC, the controller returns corrected data. On a DED, the controller generates a slave bus error. The MCRAMC implements up to four memory banks or channels. RAM must be distributed evenly across all channels.