21.5.1 Principle of Operation

The CLK_MAIN clock signal from the GCLK0 module is the source for the main clock, which in turn is the common root for the synchronous clocks for the CPU, APBx (Advanced Peripheral Bus), and AHBx (Advanced High-performance Bus).

The clocks for each module in a clock domain can be masked individually to avoid power consumption in inactive modules. Depending on the sleep mode, some clock domains can be turned off.