32.6.3.2 Partial Store and Forward Using Packet Buffer DMA
The DMA uses SRAM-based packet buffers,
and can be programmed into a low-latency mode, known as Partial Store and Forward. This
mode allows for a reduced latency as the full packet is not buffered before forwarding.
Note: This option is only available
when the device is configured for full duplex operation.
This feature is enabled through the programmable TX and RX
Partial Store and Forward registers (TPSF and RPSF). When the transmit Partial Store and
Forward mode is activated, the transmitter will only begin to forward the packet to the
MAC when there is enough packet data stored in the packet buffer. Likewise, when the
receive Partial Store and Forward mode is activated, the receiver will only begin to
forward the packet to the AHB when enough packet data is stored in the packet buffer.
The amount of packet data required to activate the forwarding process is programmable
through watermark registers. These registers are located at the same address as the
partial store and forward enable bits.
Note:
- The minimum operational value for the TX partial store and forward watermark is 20. There is no operational limit for the RX partial store and forward watermark.
- Limit maximum length buffers sent in each individual BD to 56 bytes, that is less than the TX SRAM space allocated to the queue to which LSO frames are being queued. For example, if LSO frames are being queued to Q0, and 16 KB has been allocated to Q0 (as part of hardware configuration), then limit the length field within each queued BD to a maximum of 16327 bytes (i.e., the issue can occur if the length field is set in the range 16328 to 16383).
Enabling Partial Store and Forward is a useful means to reduce latency, but there are performance implications. The ETH DMA uses separate transmit and receive lists of buffer descriptors, with each descriptor describing a buffer area in memory. This allows Ethernet packets to be broken up and scattered around the AHB memory space.