3.4.1 Sleep Modes

Some clarifications has been made to tables 13-2 and 13-4 in the Functional Description - Operation - Sleep Modes section.

Table 13-2. Sleep Mode Activity for Peripherals

ClockPeripheralActive in Sleep Mode
IdleStandbyPower-Down
HTLLEN=0HTLLEN=1
CLK_CPUCPU----
CLK_RTCRTCXX(1,2)X(2)X(2)
CLK_WDTWDTXXXX
CLK_BOD(3)BODXXXX
-(4) CCLXX(1)--
CLK_PEREVSYSXXXX
NVM(5)XXXX
ACnXX(1)--
ADCn
DACn
OPAMP
TCAn
TCBn
ZCDn
All other peripheralsX---
Note:
  1. For the peripheral to run in Standby sleep mode, the RUNSTDBY bit of the corresponding peripheral must be set
  2. In Standby sleep mode, only the RTC functionality requires the RUNSTDBY bit to be set. In Power-Down sleep mode, only the PIT functionality is available.
  3. CLK_BOD is required only when the BOD is running in Sampled mode
  4. The clock domain depends on the clock source selected for CCL
  5. Programming in progress will be completed, then the NVM peripheral will be disabled

Table 13-4. Sleep Mode Wake-up Sources

Wake-Up SourcesActive in Sleep Mode
IdleStandbyPower-Down
HTLLEN=0HTLLEN=1
PORT Pin interruptXX(1)X(1)X(1)
BOD VLM interruptXXXX
MVIO interruptsXXXX
RTC interruptsXX(2,3)X(3)X(3)
TWI Address Match interruptXXX-
CCL interruptsXX(2)X(4)-
USART Start-Of-Frame interruptXX--
TCAn interruptsXX(2)--
TCBn interrupts
ADCn interrupts
ACn interrupts
ZCD interrupts
All other interruptsX---
Note:
  1. The I/O pin must be configured according to Asynchronous Sensing Pin Properties in the PORT section
  2. For the peripheral to run in Standby sleep mode, the RUNSTDBY bit of the corresponding peripheral must be set
  3. In Standby sleep mode, only the RTC functionality requires the RUNSTDBY bit to be set. In Power-Down sleep mode, only the PIT functionality is available.
  4. CCL will only wake up the device if the path through LUTn is asynchronous (FILTSEL=0x0 and EDGEDET=0x0 in the CCL.LUTnCTRLA register)