1 Silicon Issue Summary

Legend

-
Erratum is not applicable.
X
Erratum is applicable.
PeripheralShort DescriptionValid for Silicon Revision
Rev. A4(1)Rev. A5Rev. B0
Device Some Reserved Fuse Bits Are ‘1 X--
Increased Current Consumption May Occur When VDD Drops XX-
CRC Check During Reset Initialization Is not Functional X--
Write Operation Lost if Consecutive Writes to Specific Address Spaces XXX
ADC Increased Offset in Single-Ended Mode X--
ADC MUX Selection and Accumulation Number has Delayed Update When Initialization Delay is Used XXX
CCL The CCL Must be Disabled to Change the Configuration of a Single LUT XX-
The LINK Input Source Selection for LUT3 Is not Functional on 28- and 32-Pin Devices X--
CLKCTRL External Clock/Crystal Status Bit is Not Set When the External Clock Source is Ready X--
RUNSTDBY is Not Functional When Using External Clock Sources X--
PLL Status not Working as Expected XX-
The PLL Will Not Run when Using XOSCHF with an External Crystal XX-
DAC DAC Output Buffer Lifetime Drift XX-
NVMCTRL Flash Multi-Page Erase Can Erase Write Protected Section XX-
NVM_EEPROM_ERASE Command does Not Respect Write Protect XXX
OPAMP OPAMP Consume More Power Than Expected X--
The Input Range Select is Read-Only X--
PORT PD0 Input Buffer is Floating XXX
RSTCTRL BOD Registers not Reset When UPDI Is Enabled X--
SPI Alternative 2 Pin Position is Non-Functional for SPI1 with 48-Pin Devices XX-
TCA Restart Will Reset Counter Direction in NORMAL and FRQ Mode XX-
TCB CCMP and CNT Registers Act as 16-Bit Registers in 8-Bit PWM Mode XX-
TCB4 Waveform Output Alternative 1 Non-Functional XXX
TCD Asynchronous Input Events not Working When TCD Counter Prescaler Is Used XX-
CMPAEN Controls All WOx for Alternative Pin Functions XX-
Halting TCD and Waiting for SW Restart Does Not Work if Compare Value A is 0 or Dual Slope Mode is Used XXX
TWI The Output Pin Override Does not Function as Expected XX-
Flush Non-Functional XXX
USART Open-Drain Mode Does not Work When TXD Is Configured as Output XX-
Start-of-Frame Detection Can Unintentionally Be Triggered in Active Mode XX-
Receiver Non-Functional after Detection of Inconsistent Synchronization Field XXX
ZCD All ZCD Output Selection Bits Are Tied to the ZCD0 Bit X--
Note:
  1. This revision is the initial release of the silicon.