Device |
Some Reserved Fuse Bits Are ‘1 ’
| X | - | - |
Increased Current Consumption May Occur When VDD Drops
| X | X | - |
CRC Check During Reset Initialization Is not Functional
| X | - | - |
Write Operation Lost if Consecutive Writes to Specific Address Spaces
| X | X | X |
ADC |
Increased Offset in Single-Ended Mode
| X | - | - |
ADC MUX Selection and Accumulation Number has Delayed Update When Initialization Delay is Used
| X | X | X |
CCL |
The CCL Must be Disabled to Change the Configuration of a Single LUT
| X | X | - |
The LINK Input Source Selection for LUT3 Is not Functional on 28- and 32-Pin Devices
| X | - | - |
CLKCTRL |
External Clock/Crystal Status Bit is Not Set When the External Clock Source is Ready
| X | - | - |
RUNSTDBY is Not Functional When Using External Clock Sources
| X | - | - |
PLL Status not Working as Expected
| X | X | - |
The PLL Will Not Run when Using XOSCHF with an External Crystal
| X | X | - |
DAC |
DAC Output Buffer Lifetime Drift
| X | X | - |
NVMCTRL |
Flash Multi-Page Erase Can Erase Write Protected Section
| X | X | - |
NVM_EEPROM_ERASE Command does Not Respect Write Protect
| X | X | X |
OPAMP |
OPAMP Consume More Power Than Expected
| X | - | - |
The Input Range Select is Read-Only
| X | - | - |
PORT |
PD0 Input Buffer is Floating
| X | X | X |
RSTCTRL |
BOD Registers not Reset When UPDI Is Enabled
| X | - | - |
SPI |
Alternative 2 Pin Position is Non-Functional for SPI1 with 48-Pin Devices
| X | X | - |
TCA |
Restart Will Reset Counter Direction in NORMAL and FRQ Mode
| X | X | - |
TCB |
CCMP and CNT Registers Act as 16-Bit Registers in 8-Bit PWM Mode
| X | X | - |
TCB4 Waveform Output Alternative 1 Non-Functional
| X | X | X |
TCD |
Asynchronous Input Events not Working When TCD Counter Prescaler Is Used
| X | X | - |
CMPAEN Controls All WOx for Alternative Pin Functions
| X | X | - |
Halting TCD and Waiting for SW Restart Does Not Work if Compare Value A is 0 or Dual Slope Mode is Used
| X | X | X |
TWI |
The Output Pin Override Does not Function as Expected
| X | X | - |
Flush Non-Functional
| X | X | X |
USART |
Open-Drain Mode Does not Work When TXD Is Configured as Output
| X | X | - |
Start-of-Frame Detection Can Unintentionally Be Triggered in Active Mode
| X | X | - |
Receiver Non-Functional after Detection of Inconsistent Synchronization Field
| X | X | X |
ZCD |
All ZCD Output Selection Bits Are Tied to the ZCD0 Bit
| X | - | - |