19.12.4 Security of Peripheral Bus Clients

The security type of a peripheral bus client is set at hardware design among the following:

  • Always Secure (AS)
  • Never Secure (NS)
  • Programmable Secure (PS)

To configure the security mode required for accessing a peripheral bus client connected to the system-to-peripheral bus bridge (HBRIDGE), the MATRIX features three 32-bit Security Peripheral Select x Registers. Some of these bits may have been set to a secure or a non-secure value by design, whereas others are programmed by software (see Security Peripheral Select x Registers).

Peripheral security state, “secure” or “non-secure” is an AND operation between H32MX MATRIX_SPSELRx and H64MX MATRIX_SPSELRx for the bit corresponding to the peripheral.

As a general rule:

  • The peripheral security state is applied to the corresponding peripheral interrupt line. Exceptions may occur on some peripherals (PIO Controller, etc.). In such case, refer to the peripheral description.
  • The peripheral security state is applied to the peripheral host part, if any. Exceptions may occur on some peripherals. In such case, refer to the peripheral description. See Security Types of System Bus Hosts.

MATRIX_SPSELRx bits in the H32MX or H64MX user interface are respectively read/write or read-only to ‘1’ depending on whether the peripheral is connected or not, on the matrix.

All bit values in the following table except those marked ‘UD’ (User Defined) are read-only and cannot be changed. Values marked ‘UD’ can be changed. Refer to the following examples.

  • Example for GMAC, Peripheral ID 5, which is connected to the H32MX Matrix
    • H64MX MATRIX_SPSELR1[5] = 1 (read-only); no influence on the security configuration
    • H32MX MATRIX_SPSELR1[5] can be written by user to program the security.
  • Example for LCDC, Peripheral ID 45, which is connected to the H64MX Matrix
    • H64MX MATRIX_SPSELR2[13] can be written by user to program the security.
    • H32MX MATRIX_SPSELR2[13] = 1 (read-only); no influence on the security configuration
  • Example for AIC, Peripheral ID 49, which is connected to the H32MX Matrix
    • H64MX MATRIX_SPSELR2[17] = 1 (read-only); sets the peripheral as Non-secure by hardware, also called “Never Secure”
    • H32MX MATRIX_SPSELR2[17] = 1 (read-only); no influence on the security configuration
  • Example for SAIC, Peripheral ID 0, which is connected to the H32MX Matrix
    • H64MX MATRIX_SPSELR1[0] = 1 (read-only); no influence on the security configuration
    • H32MX MATRIX_SPSELR1[0] = 0 (read-only); sets the peripheral as Secure by hardware, also called “Always Secure”

The system-to-peripheral bus bridge compares the incoming host request security bit with the required security mode for the selected peripheral, and accepts or denies access. In the last case, its bus error response is internally flagged in MATRIX_MESR; the offending address is registered in MATRIX_MEAR so that the client and the targeted protected region are also known.

Table 19-9. Peripheral Identifiers
Instance IDInstance NameInternal InterruptPMC Clock ControlInstance DescriptionClock TypeSecurity(1)In MatrixMATRIX_SPSELRx BitBit Value in H32MXBit Value in H64MX
0SAICFIQ–FIQ Interrupt IDSYS_CLK_LSAS–MATRIX_SPSELR1[0]01
1PMCX–Power Management ControllerSYS_CLOCKPSH64MXMATRIX_SPSELR1[1]1UD
2ARMPMUXPerformance Monitor Unit (PMU)PROC_CLKPSH64MXMATRIX_SPSELR1[2]1UD
3PITX–Periodic Interval Timer InterruptSYS_CLK_LSPS(3)H32MXMATRIX_SPSELR1[3] ––
4WDTX–Watchdog Timer InterruptSYS_CLK_LSPS(3)H32MXMATRIX_SPSELR1[4] ––
5GMACXXEthernet MACHCLOCK_LS PCLOCK_LSPSH32MXMATRIX_SPSELR1[5]UD1
6XDMAC0XXDMA Controller 0HCLOCK_HSPSH64MXMATRIX_SPSELR1[6]1UD
7XDMAC1XXDMA Controller 1HCLOCK_HSPSH64MXMATRIX_SPSELR1[7]1UD
8ICMXXIntegrity Check MonitorHCLOCK_LSPSH32MXMATRIX_SPSELR1[8]UD1
9AESXXAdvanced Encryption StandardPCLK_HSPSH64MXMATRIX_SPSELR1[9]1UD
10AESBXXAES BridgeHCLOCK_HSPSH64MXMATRIX_SPSELR1[10]1UD
11TDESXXTriple Data Encryption Standard PCLOCK_LSPSH32MXMATRIX_SPSELR1[11]UD1
12SHAXXSHA SignaturePCLK_HSPSH64MXMATRIX_SPSELR1[12]1UD
13MPDDRCXXMPDDR ControllerHCLOCK_HSPSH64MXMATRIX_SPSELR1[13]1UD
14H32MXXX32-bit MatrixSYS_CLK_LSAS–MATRIX_SPSELR1[14]01
15H64MXXX64-bit MatrixSYS_CLOCKAS–MATRIX_SPSELR1[15]10
16SECUMODXXSecurity ModuleSLOW_CLOCKASH32MXMATRIX_SPSELR1[16]01
17HSMCXXMultibit ECC InterruptHCLOCK_LSPSH32MXMATRIX_SPSELR1[17]UD1
18PIOAXXParallel I/O ControllerPCLOCK_LSASH32MXMATRIX_SPSELR1[18]01
19FLEXCOM0XXFLEXCOM 0PCLOCK_LSPSH32MXMATRIX_SPSELR1[19]UD1
20FLEXCOM1XXFLEXCOM 1PCLOCK_LSPSH32MXMATRIX_SPSELR1[20]UD1
21FLEXCOM2XXFLEXCOM 2PCLOCK_LSPSH32MXMATRIX_SPSELR1[21]UD1
22FLEXCOM3XXFLEXCOM 3PCLOCK_LSPSH32MXMATRIX_SPSELR1[22]UD1
23FLEXCOM4XXFLEXCOM 4PCLOCK_LSPSH32MXMATRIX_SPSELR1[23]UD1
24UART0XXUniversal Asynchronous Receiver Transmitter 0PCLOCK_LSPSH32MXMATRIX_SPSELR1[24]UD1
25UART1XXUniversal Asynchronous Receiver Transmitter 1PCLOCK_LSPSH32MXMATRIX_SPSELR1[25]UD1
26UART2XXUniversal Asynchronous Receiver Transmitter 2PCLOCK_LSPSH32MXMATRIX_SPSELR1[26]UD1
27UART3XXUniversal Asynchronous Receiver Transmitter 3PCLOCK_LSPSH32MXMATRIX_SPSELR1[27]UD1
28UART4XXUniversal Asynchronous Receiver Transmitter 4PCLOCK_LSPSH32MXMATRIX_SPSELR1[28]UD1
29TWIHS0XXTwo-Wire Interface 0PCLOCK_LSPSH32MXMATRIX_SPSELR1[29]UD1
30TWIHS1XXTwo-Wire Interface 1PCLOCK_LSPSH32MXMATRIX_SPSELR1[30]UD1
31SDMMC0XXSecure Digital MultiMedia Card Controller 0HCLOCK_HSPSH64MXMATRIX_SPSELR1[31]1UD
32SDMMC1XXSecure Digital MultiMedia Card Controller 1HCLOCK_HSPSH64MXMATRIX_SPSELR2[0]1UD
33SPI0XXSerial Peripheral Interface 0PCLOCK_LSPSH32MXMATRIX_SPSELR2[1]UD1
34SPI1XXSerial Peripheral Interface 1PCLOCK_LSPSH32MXMATRIX_SPSELR2[2]UD1
35TC0XXTimer Counter 0 (ch. 0, 1, 2)PCLOCK_LSPSH32MXMATRIX_SPSELR2[3]UD1
36TC1XXTimer Counter 1 (ch. 3, 4, 5)PCLOCK_LSPSH32MXMATRIX_SPSELR2[4]UD1
37––––––––––
38PWMXXPulse Width Modulation Controller 0 (ch. 0, 1, 2, 3)PCLOCK_LSPSH32MXMATRIX_SPSELR2[6]UD1
39––––––––––
40ADCXXTouchscreen ADC ControllerPCLOCK_LSPSH32MXMATRIX_SPSELR2[8]UD1
41UHPHSXXUSB Host High-SpeedHCLOCK_LSPSH32MXMATRIX_SPSELR2[9]UD1
42UDPHSXXUSB Device High-SpeedHCLOCK_LSPSH32MXMATRIX_SPSELR2[10]UD1
43SSC0XXSynchronous Serial Controller 0PCLOCK_LSPSH32MXMATRIX_SPSELR2[11]UD1
44SSC1XXSynchronous Serial Controller 1PCLOCK_LSPSH32MXMATRIX_SPSELR2[12]UD1
45LCDCXXLCD ControllerHCLOCK_HSPSH64MXMATRIX_SPSELR2[13]1UD
46ISCXXImage Sensor ControllerHCLOCK_HSPSH64MXMATRIX_SPSELR2[14]1UD
47TRNGXXTrue Random Number GeneratorPCLOCK_LSPSH32MXMATRIX_SPSELR2[15]UD1
48PDMICXXPulse Density Modulation Interface ControllerPCLOCK_LSPSH32MXMATRIX_SPSELR2[16]UD1
49AICIRQ–IRQ Interrupt IDSYS_CLK_LSNSH32MXMATRIX_SPSELR2[17]11
50SFCXXSecure Fuse ControllerPCLOCK_LSPSH32MXMATRIX_SPSELR2[18]UD1
51SECURAMXXSecure RAMPCLOCK_LSASH32MXMATRIX_SPSELR2[19]01
52QSPI0XXQuad SPI Interface 0HCLOCK_HSPSH64MXMATRIX_SPSELR2[20]1UD
53QSPI1XXQuad SPI Interface 1HCLOCK_HSPSH64MXMATRIX_SPSELR2[21]1UD
54I2SC0XXInter-IC Sound Controller 0PCLOCK_LSPSH32MXMATRIX_SPSELR2[22]UD1
55I2SC1XXInter-IC Sound Controller 1PCLOCK_LSPSH32MXMATRIX_SPSELR2[23]UD1
56MCAN0INT0XMCAN 0 Interrupt0HCLOCK_LSPSH32MXMATRIX_SPSELR2[24]UD1
57MCAN1INT0XMCAN 1 Interrupt0HCLOCK_LSPSH32MXMATRIX_SPSELR2[25]UD1
58PTCXXPeripheral Touch Controller PCLOCK_LSPSH32MXMATRIX_SPSELR2[26]UD1
59CLASSDXXAudio Class D AmplifierPCLOCK_LSPSH32MXMATRIX_SPSELR2[27]UD1
60SFR––Special Function Register(2)SYS_CLK_LSPSH32MXMATRIX_SPSELR2[28]UD1
61SAIC––Secure Advanced Interrupt Controller(2)SYS_CLK_LSASH32MXMATRIX_SPSELR2[29]01
62AIC––Advanced Interrupt Controller(2)SYS_CLK_LSNSH32MXMATRIX_SPSELR2[30]11
63L2CCX–L2 Cache Controller–PSH64MXMATRIX_SPSELR2[31]1UD
64MCAN0INT1–MCAN 0 Interrupt1–PSH32MXMATRIX_SPSELR3[0]UD1
65MCAN1INT1–MCAN 1 Interrupt1–PSH32MXMATRIX_SPSELR3[1]UD1
66GMACQ1–GMAC Queue 1 Interrupt–PSH32MXMATRIX_SPSELR3[2]UD1
67GMACQ2–GMAC Queue 2 Interrupt–PSH32MXMATRIX_SPSELR3[3]UD1
68PIOBX–––ASH32MXMATRIX_SPSELR3[4]01
69PIOCX–––ASH32MXMATRIX_SPSELR3[5]01
70PIODX–––ASH32MXMATRIX_SPSELR3[6]01
71SDMMC0TIMER–––PSH32MXMATRIX_SPSELR3[7]UD1
72SDMMC1TIMER–––PSH32MXMATRIX_SPSELR3[8]UD1
73RSTCX–Reset ControllerSYS_CLK_LSPS(3)H32MXMATRIX_SPSELR3[9]––
74SYSC, RTCX–System Controller InterruptSYS_CLK_LSPS(3)H32MXMATRIX_SPSELR3[10]UD1
75ACCX–Analog ComparatorSYS_CLK_LSPSH32MXMATRIX_SPSELR3[11]UD1
76RXLPX–UART Low-PowerSYS_CLK_LSPSH32MXMATRIX_SPSELR3[12]UD1
77SFRBU––Special Function Register Backup(2)–PSH32MXMATRIX_SPSELR3[13]UD1
78CHIPID––Chip ID–PSH32MXMATRIX_SPSELR3[14]UD1
Note:
  1. AS = Always Secure; PS = Programmable Secure; NS = Never Secure.
  2. For security purposes, there is no matching clock but a peripheral ID only.
  3. The PIT, RSTC and WDT register accesses are controlled by the RTC. They are in Secure mode if the RTC is in Secure mode; they are in Non-secure mode if the RTC is in Non-secure mode.