47.9.5.4.4.2 — Clock Stretching in Write Mode
The clock is tied low if the internal shifter and FLEX_TWI_RHR are full. If a STOP or REPEATED_START condition was not detected, it is tied low until FLEX_TWI_RHR is read.
The following figure describes the clock stretching in Write mode.
![](GUID-7BAD77B8-A45D-46DE-9390-4B8DC7DFE8DD-low.png)
Note:
- At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR.
- SCLWS is automatically set when the clock stretching mechanism is started and automatically reset when the mechanism is finished.