55.7.7 PDMIC Interrupt Status Register
| Name: | PDMIC_ISR |
| Offset: | 0x24 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| OVRE | DRDY | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FIFOCNT[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bit 25 – OVRE Overrun Error (cleared on read)
| Value | Description |
|---|---|
| 0 | No overrun error has occurred since the last read of PDMIC_ISR. |
| 1 | At least one overrun error has occurred since the last read of PDMIC_ISR. |
Bit 24 – DRDY Data Ready (cleared by reading PDMIC_CDR)
| Value | Description |
|---|---|
| 0 | No data has been converted since the last read of PDMIC_CDR. |
| 1 | At least one data has been converted and is available in PDMIC_CDR. |
Bits 23:16 – FIFOCNT[7:0] FIFO Count
Number of conversions available in the FIFO (not a source of interrupt).