54.3 Block Diagram

Table 54-1. Timer Counter Clock Assignment
NameDefinition
TIMER_CLOCK1GCLK [35], GCLK [36]
TIMER_CLOCK2System bus clock divided by 8
TIMER_CLOCK3System bus clock divided by 32
TIMER_CLOCK4System bus clock divided by 128
TIMER_CLOCK5 (See Note) TD_SLCK
Note:
  1. The GCLK frequency must be at least three times lower than peripheral clock frequency.
Figure 54-1. TC Block Diagram
Note:
  1. This figure provides pin names of a first instance of a Timer Counter block (i.e., instance TC0). For any subsequent instances, the signal numbering increments. For example, “TCLK3-TCLK5”, "TIOA3-TIOA5” and "TIOB3-TIOB5” are the external clock input pins of a second Timer Counter block (i.e., instance TC1).
  2. The QDEC connections are detailed in Figure 54-17.
Table 54-2. Channel Signal Description
Signal NameDescription
XC0, XC1, XC2Channel clock source that can be connected to TIOAx, TIOBx, TCLKx
TIMER_CLOCK1-5Channel clock source from system clocks
TIOAx

Capture mode: Timer Counter input


Waveform mode: Timer Counter output

TIOBx

Capture mode: Timer Counter input


Waveform mode: Timer Counter input/output

INTInterrupt signal output (internal signal)
SYNCSynchronization input signal (from Configuration register)