37.18.1 MLC/SLC Write Page Operation Using PMECC

When an MLC write page operation is performed, the PMECC controller is configured with the NANDWR bit of the PMECC Configuration (HSMC_PMECCFG) register set to one. When the NAND spare area contains file system information and redundancy (PMECCx), the spare area is error-protected, then the HSMC_PMECCFG.SPAREEN bit is set. When the NAND spare area contains only redundancy information, the SPAREEN bit is cleared.

When the write page operation is terminated, the user writes the redundancy in the NAND spare area. This operation can be done with DMA assistance.

Table 37-13. Relevant Redundancy Registers
BCH_ERR FieldSector Size Set to 512 BytesSector Size Set to 1024 Bytes
0PMECC0PMECC0
1PMECC0, PMECC1PMECC0, PMECC1
2PMECC0, PMECC1, PMECC2, PMECC3PMECC0, PMECC1, PMECC2, PMECC3
3PMECC0, PMECC1, PMECC2, PMECC3, PMECC4, PMECC5, PMECC6PMECC0, PMECC1, PMECC2, PMECC3, PMECC4, PMECC5, PMECC6
4PMECC0, PMECC1, PMECC2, PMECC3, PMECC4, PMECC5, PMECC6, PMECC7, PMECC8, PMECC9PMECC0, PMECC1, PMECC2, PMECC3, PMECC4, PMECC5, PMECC6, PMECC7, PMECC8, PMECC9, PMECC10
5PMECC0, PMECC1, PMECC2, PMECC3, PMECC4, PMECC5, PMECC6, PMECC7, PMECC8, PMECC9, PMECC10, PMECC11, PMECC12PMECC0, PMECC1, PMECC2, PMECC3, PMECC4, PMECC5, PMECC6, PMECC7, PMECC8, PMECC9, PMECC10, PMECC11, PMECC12, PMECC13
Table 37-14. Number of Relevant ECC Bytes per Sector, Copied from LSByte to MSByte
BCH_ERR FieldSector Size Set to 512 BytesSector Size Set to 1024 Bytes
04 bytes4 bytes
17 bytes7 bytes
213 bytes14 bytes
320 bytes21 bytes
439 bytes42 bytes
552 bytes56 bytes