37.18.1 MLC/SLC Write Page Operation Using PMECC

When an MLC write page operation is performed, the PMECC controller is configured with the NANDWR bit of the PMECC Configuration (HSMC_PMECCFG) register set to one. When the NAND spare area contains file system information and redundancy (PMECCx), the spare area is error-protected, then the HSMC_PMECCFG.SPAREEN bit is set. When the NAND spare area contains only redundancy information, the SPAREEN bit is cleared.

When the write page operation is terminated, the user writes the redundancy in the NAND spare area. This operation can be done with DMA assistance.

Table 37-13. Relevant Redundancy Registers
BCH_ERR Field Sector Size Set to 512 Bytes Sector Size Set to 1024 Bytes
0 PMECC0 PMECC0
1 PMECC0, PMECC1 PMECC0, PMECC1
2 PMECC0, PMECC1, PMECC2, PMECC3 PMECC0, PMECC1, PMECC2, PMECC3
3 PMECC0, PMECC1, PMECC2, PMECC3, PMECC4, PMECC5, PMECC6 PMECC0, PMECC1, PMECC2, PMECC3, PMECC4, PMECC5, PMECC6
4 PMECC0, PMECC1, PMECC2, PMECC3, PMECC4, PMECC5, PMECC6, PMECC7, PMECC8, PMECC9 PMECC0, PMECC1, PMECC2, PMECC3, PMECC4, PMECC5, PMECC6, PMECC7, PMECC8, PMECC9, PMECC10
5 PMECC0, PMECC1, PMECC2, PMECC3, PMECC4, PMECC5, PMECC6, PMECC7, PMECC8, PMECC9, PMECC10, PMECC11, PMECC12 PMECC0, PMECC1, PMECC2, PMECC3, PMECC4, PMECC5, PMECC6, PMECC7, PMECC8, PMECC9, PMECC10, PMECC11, PMECC12, PMECC13
Table 37-14. Number of Relevant ECC Bytes per Sector, Copied from LSByte to MSByte
BCH_ERR Field Sector Size Set to 512 Bytes Sector Size Set to 1024 Bytes
0 4 bytes 4 bytes
1 7 bytes 7 bytes
2 13 bytes 14 bytes
3 20 bytes 21 bytes
4 39 bytes 42 bytes
5 52 bytes 56 bytes