37.17.2 NFC Control Registers

NAND Flash Read and NAND Flash Program operations can be performed through the NFC Command registers. In order to minimize CPU intervention and latency, commands are posted in a command buffer. This buffer provides zero wait state latency.

The NFC handles an automatic transfer between the external NAND Flash and the chip via the NFC SRAM. The transfer is done by programming NFC Command registers.

NFC Command registers are very efficient. When writing to these registers:

  • the address of the register (NFCADDR_CMD) is the command used,
  • the data of the register (NFCDATA_ADDT) is the address to be sent to the NAND Flash.

In one single access, the command is sent and immediately executed by the NFC. Two commands can even be programmed within a single access (CMD1, CMD2) depending on the VCMD2 value.

The NFC can send up to five address cycles.

The figure below shows a typical NAND Flash Page Read Command of a NAND Flash Memory and correspondence with the NFC Address Command register.

Figure 37-31. NFC/NAND Flash Access Example

For more details, see NFCADDR_CMD.

Reading the NFC Command register (to any address) gives the status of the NFC. This is especially useful to know if the NFC is busy, for example.