39.2 Embedded Characteristics

  • Dual System Bus Host Interface
  • Supports Single Scan Active TFT Display
  • Supports 12-, 16-, 18- and 24-bit Output Mode
  • Supports Spatial Dithering for 12-, 16-, 18-bit Output Mode
  • Asynchronous Output Mode Supported
  • 1, 2, 4, 8 bits per Pixel (Palletized)
  • 12, 16, 18, 19, 24, 25 and 32 bits per Pixel (Non-palletized)
  • Supports One Base Layer (Background)
  • Supports Overlay 1 Layer
  • Supports Overlay 2 Layer
  • Supports High-End Overlay (HEO) Layer
  • High-End Overlay supports 4:2:0 Planar Mode and Semiplanar Mode
  • High-End Overlay supports 4:2:2 Planar Mode, Semiplanar Mode and Packed
  • High-End Overlay includes Chroma Upsampling Unit
  • Little Endian Memory Organization
  • Programmable Timing Engine, with Integer Clock Divider
  • Programmable Polarity for Data, Line Synchro and Frame Synchro
  • Up to 1024x768 (XGA) with Overlay (Application-Dependent). Still Image up to WXGA.
  • Color Lookup Table with up to 256 Entries and Predefined 8-bit Alpha
  • Programmable Negative and Positive Row Striding for all Layers
  • Programmable Negative and Positive Pixel Striding for Layers
  • Horizontal and Vertical Rescaling Unit with Edge Interpolation and Independent Non-Integer Ratio, up to 1024x768
  • Hidden Layer Removal supported
  • Integrates Fully Programmable Color Space Conversion
  • Blender Function Supports Arbitrary 8-bit Alpha Value and Chroma Keying
  • DMA User Interface uses Linked List Structure and Add-to-queue Structure