50.2 Embedded Characteristics

  • Host SPI Interface
    • Programmable clock phase and clock polarity
    • Programmable transfer delays between consecutive transfers, between clock and data, between deactivation and activation of chip select
  • SPI Mode
    • Interface to serial peripherals such as ADCs, DACs, LCD controllers, CAN controllers and sensors
    • 8-bit/16-bit/32-bit programmable data length
  • Serial Memory Mode
    • Interface to serial Flash memories operating in Single-bit SPI, Dual SPI and Quad SPI
    • Interface to serial Flash Memories operating in Single Data Rate Mode
    • Supports “Execute In Place” (XIP)— code execution by the system directly from a serial Flash memory
    • Flexible instruction register for compatibility with all serial Flash memories
    • 32-bit address mode (default is 24-bit address) to support serial Flash memories larger than 128 Mbits
    • Continuous read mode
    • Scrambling/unscrambling “On-The-Fly”
  • Connection to DMA Channel Capabilities Optimizes Data Transfers
    • One channel for the receiver, one channel for the transmitter
  • Register Write Protection