48.6.6 UART Interrupt Status Register
| Name: | UART_SR |
| Offset: | 0x14 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CMP | TXEMPTY | TIMEOUT | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PARE | FRAME | OVRE | TXRDY | RXRDY | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 15 – CMP Comparison Match (Cleared by writing UART_CR.RSTSTA)
| Value | Description |
|---|---|
| 0 | No received character matches the comparison criteria programmed in VAL1, VAL2 fields and in CMPPAR bit since the last RSTSTA. |
| 1 | The received character matches the comparison criteria. |
Bit 9 – TXEMPTY Transmitter Empty (Cleared by writing UART_THR)
| Value | Description |
|---|---|
| 0 | There are characters in UART_THR, or characters being processed by the transmitter, or the transmitter is disabled. |
| 1 | There are no characters in UART_THR and there are no characters being processed by the transmitter. |
Bit 8 – TIMEOUT Receiver Time-out (Cleared by writing UART_CR.STTTO)
| Value | Description |
|---|---|
| 0 | There has not been a time-out since the last Start Time-out command (STTTO in UART_CR) or the Time-out register is 0. |
| 1 | There has been a time-out since the last Start Time-out command (STTTO in UART_CR). |
Bit 7 – PARE Parity Error (Cleared by writing UART_CR.RSTSTA)
| Value | Description |
|---|---|
| 0 | No parity error has occurred since the last RSTSTA. |
| 1 | At least one parity error has occurred since the last RSTSTA. |
Bit 6 – FRAME Framing Error (Cleared by writing UART_CR.RSTSTA)
| Value | Description |
|---|---|
| 0 | No framing error has occurred since the last RSTSTA. |
| 1 | At least one framing error has occurred since the last RSTSTA. |
Bit 5 – OVRE Overrun Error (Cleared by writing UART_CR.RSTSTA)
| Value | Description |
|---|---|
| 0 | No overrun error has occurred since the last RSTSTA. |
| 1 | At least one overrun error has occurred since the last RSTSTA. |
Bit 1 – TXRDY Transmitter Ready (Cleared by writing UART_THR)
| Value | Description |
|---|---|
| 0 | A character has been written to UART_THR and not yet transferred to the internal shift register, or the transmitter is disabled. |
| 1 | There is no character written to UART_THR not yet transferred to the internal shift register. |
Bit 0 – RXRDY Receiver Ready (Cleared by reading UART_RHR)
| Value | Description |
|---|---|
| 0 | No character has been received since the last read of the UART_RHR, or the receiver is disabled. |
| 1 | At least one complete character has been received, transferred to UART_RHR and not yet read. |