41.6.4 USB Transfer Event Definitions
A transfer is composed of one or several transactions as shown in the table below.
Transfer | Transaction | |
---|---|---|
Direction | Type | |
CONTROL (bidirectional) | Control Transfer (1) |
|
IN (device toward host) | Bulk IN Transfer |
|
Interrupt IN Transfer |
|
|
Isochronous IN Transfer (2) |
|
|
OUT (host toward device) | Bulk OUT Transfer |
|
Interrupt OUT Transfer |
|
|
Isochronous OUT Transfer (2) |
|
Note:
- Control transfer must use endpoints with one bank and can be aborted using a stall handshake.
- Isochronous transfers must use endpoints configured with two or three banks.
An endpoint handles all transactions related to the type of transfer for which it has been configured.
Endpoint # | Mnemonic | Nb Banks | DMA | High Bandwidth | Max. Endpoint Size | Endpoint Type |
---|---|---|---|---|---|---|
0 | EPT_0 | 1 | N | N | 64 | Control |
1 | EPT_1 | 3 | Y | Y | 1024 | Ctrl/Bulk/Iso(1)/Interrupt |
2 | EPT_2 | 3 | Y | Y | 1024 | Ctrl/Bulk/Iso(1)/Interrupt |
3 | EPT_3 | 2 | Y | N | 1024 | Ctrl/Bulk/Iso(1)/Interrupt |
4 | EPT_4 | 2 | Y | N | 1024 | Ctrl/Bulk/Iso(1)/Interrupt |
5 | EPT_5 | 2 | Y | N | 1024 | Ctrl/Bulk/Iso(1)/Interrupt |
6 | EPT_6 | 2 | Y | N | 1024 | Ctrl/Bulk/Iso(1)/Interrupt |
7 | EPT_7 | 2 | Y | N | 1024 | Ctrl/Bulk/Iso(1)/Interrupt |
8 | EPT_8 | 2 | N | N | 1024 | Ctrl/Bulk/Iso(1)/Interrupt |
9 | EPT_9 | 2 | N | N | 1024 | Ctrl/Bulk/Iso(1)/Interrupt |
10 | EPT_10 | 2 | N | N | 1024 | Ctrl/Bulk/Iso(1)/Interrupt |
11 | EPT_11 | 2 | N | N | 1024 | Ctrl/Bulk/Iso(1)/Interrupt |
12 | EPT_12 | 2 | N | N | 1024 | Ctrl/Bulk/Iso(1)/Interrupt |
13 | EPT_13 | 2 | N | N | 1024 | Ctrl/Bulk/Iso(1)/Interrupt |
14 | EPT_14 | 2 | N | N | 1024 | Ctrl/Bulk/Iso(1)/Interrupt |
15 | EPT_15 | 2 | N | N | 1024 | Ctrl/Bulk/Iso(1)/Interrupt |
Note:
- In Isochronous (Iso) mode, it is preferable that the high bandwidth capability is available.
The size of the internal DPRAM is 8 Kbytes.
Suspend and resume are automatically detected by the UDPHS device, which notifies the processor by raising an interrupt.