12.4 Peripheral Clock Types
The table below lists the clock types available on the embedded peripherals. Clock type suffixes HS and LS refer to Matrix (H64MX) and Matrix (H32MX), respectively.
For details on embedded peripherals, refer to the section Matrix (H64MX/H32MX).
| Clock Type | Description |
|---|---|
| HCLOCK_HS HCLOCK_LS |
AHB Clock. Managed with the PMC_PCER, PMC_PCDR, PMC_PCSR and PMC_PCR registers of Peripheral Clock.(1) |
| PCLOCK_HS PCLOCK_LS |
APB Clock. Managed with the PMC_PCER, PMC_PCDR, PMC_PCSR and PMC_PCR registers of Peripheral Clock. (1) |
| SYS_CLK_LS | This clock cannot be disabled. (2) |
| SYS_CLOCK | This clock cannot be disabled. (2) |
| PROC_CLK | The clock related to Processor Clock (PCK) and managed with the PMC_SCDR and PMC_SCSR registers of PMC System Clock |
| SLOW_CLOCK | The clock related to the backup area and the RTC and managed with the SCKC_CR. This clock can be generated either by an external 32.768 kHz crystal oscillator or by the on-chip 64 kHz RC oscillator. |
Note:
- Refer to the figure General Clock Block Diagram in the section Power Management Controller (PMC).
- Refer to the MCK clock in the figure General Clock Block Diagram in the section Power Management Controller (PMC).